Semiconductor test apparatus

A semiconductor test apparatus comprising:

• a tray housing unit configured to house a first tray housing unit configured to house untested semiconductor chips, a second tray housing unit configured to house secondary defective semiconductor chips, and a third tray housing unit configured to house non-defective semiconductor chips;
• a loader configured to locate the untested semiconductor chips supplied from the first tray housing unit on a loading set plate and load the untested semiconductor chips onto a test tray;
• a tester configured to test the untested semiconductor chips loaded on the test tray, wherein the test tray is loadable into and removable from the tester;
• an unloader configured to unload semiconductor chips loaded on the test tray taken from the tester and classify tested semiconductor chips as first defective semiconductor chips, the secondary defective semiconductor chips, and the non-defective semiconductor chips to locate the first defective semiconductor chips to a first unloading set plate, the secondary defective semiconductor chips to a second unloading set plate, and the non-defective semiconductor chips on a third unloading set plate;
• and
• a retest controller configured to respectively transfer the secondary defective semiconductor chips and the non-defective semiconductor chips to the second tray housing unit and the third tray housing unit and transfer the first defective semiconductor chips from the first unloading set plate to the loading set plate,
• wherein the loader is further configured to load the first defective semiconductor chips onto the test tray, and
• wherein the tester is further configured to retest the first defective semiconductor chips,
• wherein the loader is configured to load at least one of the first defective semiconductor chips and at least one of the untested semiconductor chips onto the test tray when the test tray is in the loader, and
• wherein the tester is configured to simultaneously test the at least one of the first defective semiconductor chips and the at least one of the untested semiconductor chips.