On-chip current sensing employing power distribution network voltage de-convolution
AssigneeOracle International Corporation
InventorSebastian Turullols
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Abstract
Systems, methods, and other embodiments are disclosed that are configured to provide on-chip current sensing by employing a power distribution network voltage de-convolution technique. A voltage signal on a voltage plane of a system-on-chip device is measured during operation of the system-on-chip device. The voltage signal derives from a power distribution network. The voltage signal is de-convolved, based at least in part on inverse convolution coefficients derived from the power distribution network, to recover a current signal being drawn by the system-on-chip device from the power distribution network.
Claims20
A method of sensing a current signal, the method comprising:
- in a system-on-chip device:
- measuring a voltage signal on a voltage plane of the system-on-chip device during operation of the system-on-chip device, wherein the voltage signal derives from a power distribution network;
- de-convolving the voltage signal, based at least in part on inverse convolution coefficients stored within memory of the system-on-chip device and derived from the power distribution network, to recover a current signal being drawn by the system-on-chip device from the power distribution network in a first clock domain, wherein the inverse convolution coefficients, the voltage signal, and a convolution operator are used to determine the current signal, wherein the de-convolving comprises:
- converting the current signal from the first clock domain in which the current signal was outputted to a second clock domain to synchronize the current signal with the second clock domain for adjusting a parameter of the power distribution network;
- determining a power consumption of the system-on-chip device based upon the current signal;
- and
- adjusting at least one of a clock rate of the system-on-chip device or a supply voltage provided by the power distribution network to the voltage plane based upon the power consumption to reduce an amount of electrical power consumed by the system-on-chip device.
A system-on-chip device, comprising:
- a voltage plane configured to carry an analog voltage signal derived from a power distribution network;
- analog-to-digital logic configured to convert the analog voltage signal to a digital voltage signal;
- de-convolution logic configured to recover a current signal, drawn by the system-on-chip device, from the digital voltage signal based at least in part on inverse convolution coefficients stored within memory of the system-on-chip device and derived from the power distribution network in a first clock domain, wherein the de-convolution logic uses the inverse convolution coefficients, the voltage signal, and a convolution operator to determine the current signal;
- synchronization logic configured to convert the current signal from the first clock domain in which the current signal was outputted to a second clock domain to synchronize the current signal with the second clock domain for adjusting a parameter of the power distribution;
- and
- power management logic configured to:
- determine a power consumption of the system-on-chip device based upon the current signal;
- and
- adjust at least one of a clock rate of the system-on-chip device or a supply voltage provided by the power distribution network to the voltage plane based upon the power consumption to reduce an amount of electrical power consumed by the system-on-chip device.
A method comprising:
- measuring a voltage signal on a voltage plane of a system-on-chip device during operation of the system-on-chip device, wherein the voltage signal derives from a power distribution network;
- de-convolving the voltage signal, based at least in part on inverse convolution coefficients stored within memory of the system-on-chip device and derived from the power distribution network, to recover a current signal being drawn by the system-on-chip device from the power distribution network in a first clock domain, wherein de-convolution logic uses the inverse convolution coefficients, the voltage signal, and a convolution operator to determine the current signal, wherein the de-convolving comprises:
- converting the current signal from the first clock domain in which the current signal was outputted to a second clock domain to synchronize the current signal with the second clock domain for adjusting a parameter of the power distribution network;
- determining a power consumption of the system-on-chip device based upon the current signal;
- and
- adjusting at least one of a clock rate of the system-on-chip device or a supply voltage provided by the power distribution network to the voltage plane based upon the power consumption to reduce an amount of electrical power consumed by the system-on-chip device.
Dependencies are inferred from the claim text.