Sensor circuit and method

A method for comparing the capacitance of a first sense capacitor to the capacitance of a second sense capacitor of a sensor circuit, the method comprising:

• using a first digital clock signal to initiate, at time T, discharge of a first integration capacitor, wherein a rate of discharge of the first integration capacitor is at least partly determined by the capacitance of the first sense capacitor;
• using a second digital clock signal to initiate, at time T+Td, discharge of a second integration capacitor, wherein a rate of discharge of the second integration capacitor is at least partly determined by the capacitance of the second sense capacitor;
• at time Teval, after initiation of discharge of the first and second integration capacitors, comparing the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor;
• and
• outputting a digital signal indicating the result of the comparison, wherein the method further comprises performing a plurality of measurements by repeating the steps of:
• initiating discharge of the first integration capacitor;
• initiating discharge of the second integration capacitor, and
• comparing the extent to which the first and second integration capacitors have discharged,
• for a plurality of values of Td, to evaluate the capacitance of the first and/or the second capacitor.

A sensor circuit comprising:

• a first subcircuit comprising:
• a first sense capacitor;
• a first integration capacitor, and
• a first clock input for receiving a first digital clock signal for initiating discharge of the first integration capacitor at time T, wherein a rate of discharge of the first integration capacitor is at least partly determined by a capacitance of the first sense capacitor;
• a second subcircuit comprising:
• a second sense capacitor;
• a second integration capacitor, and
• a second clock input for receiving a second digital clock signal for initiating discharge of the second integration capacitor at time T+Td, wherein a rate of discharge of the second integration capacitor is at least partly determined by a capacitance of the second sense capacitor,
• wherein the circuit is operable:
• at time Teval, after initiation of discharge of the first and second integration capacitors, to compare the extent to which the first and second integration capacitors have discharged, thereby to compare the capacitance of the first sense capacitor to the capacitance of the second sense capacitor;
• and
• to output a digital signal indicating the result of the comparison, wherein:
• the first subcircuit further comprises a first inverter having an input for receiving the first digital clock signal and an output connected to the first sense capacitor, wherein the first integration capacitor is connected to a power supply input of the first inverter, and
• the second subcircuit further comprises a second inverter having an input for receiving the second digital clock signal and an output connected to the second sense capacitor, wherein the second integration capacitor is connected to a power supply input of the second inverter.