US 10,119,822 B2Granted

In-band beating removal for a MEMS gyroscope

AssigneeNXP USA, Inc.

InventorsThierry Cassagnes, Hugues Beaulaton, Laurent Cornibert, Yean Ling Teo

Life of this patent

Estimating the term…

Loading patent…

Abstract

Vibration gyroscope circuitry, connectable to a vibrating MEMS gyroscope, includes drive circuitry for driving the gyroscope and a measurement circuit for providing a drive measurement signal indicating displacement of a mass along a drive axis. Sense circuitry processes a sense measurement signal of the gyroscope indicating displacement of the mass along a sense axis. A digital sample clock generator includes an oscillator for generating a master clock, a counter for counting master clock periods during one period of an input signal derived from the drive measurement signal, and a number count monitor for determining during how many input signal periods the number count stays constant and for comparing a number of constant periods with a critical number of constant periods. A frequency shifter triggers the oscillator to shift the master clock frequency whenever the monitor determines that the number of constant periods exceeds the critical number of constant periods.

Claims12

Dependent claims

A vibration gyroscope circuitry (VCIRC) connectable to a vibrating MEMS (micro-electro-mechanical-system) gyroscope (VMEMS), the circuitry comprising:

a drive circuitry (DRIVE) arranged to drive, when said vibration gyroscope circuitry (VCIRC) is connected, the vibrating MEMS gyroscope (VMEMS) and comprising a drive measurement circuit (DMU) arranged to provide a drive measurement voltage signal (DMV) forming a measure of a displacement of a gyroscope mass (M) along a drive axis;
and
a sense circuitry (SENSE) is arranged to, when said vibration gyroscope circuitry (VCIRC) is connected, process a sense measurement signal of the vibrating MEMS gyroscope (VMEMS) forming a measure for a displacement of said gyroscope mass (M) along a sense axis when said gyroscope mass (M) is being displaced along the drive axis by the drive circuitry, wherein the displacement of the gyroscope mass (M) along the sense axis occurs in the presence of angular rotation;
wherein the drive circuitry (DRIVE) further comprises a digital sample clock generator (SCG) for generating a sample clock signal (SCLK) from an input signal (FDxy) derivable from the drive measurement voltage signal (DMV), the sample clock generator (SCG) comprising:
an oscillator (HFOSC) arranged to generate a master clock (MOSC) with a master clock period (MOSC_PER) and a master clock frequency (Fclk), the oscillator being arranged to shift the master clock frequency;
a synchronization circuit (SYN) arranged to detect a start of an input signal period (FD_PER) of the input signal (FDxy) and to, upon detecting the start, generate a synchronization pulse (FD_OSC) in synchronization with the master clock (MOSC);
a counter (OSCCNTR) arranged to count master clock periods (MOSC_PER) between the synchronization pulse (FD_OSC) and a subsequent synchronization pulse (FD_OSC′) to obtain a number of the master clock periods (MOSC_PER) between the synchronization pulse (FD_OSC) and the subsequent synchronization pulse (FD_OSC′) as a number count (CNT);
a multiplier (MULT) arranged to multiply the number count with a pre-determined phase shift fraction (PhPerc) to obtain a number of trim periods (TRM);
a delay circuit (DLY) arranged to generate the sample clock signal (SLCK) with a clock signal period (SCLK_PER) corresponding to the number count (CNT) and with a delay relative to the synchronization pulse corresponding to the number of trim periods (TRM);
a number count monitor (NCM) arranged to determine during how many input signal periods the number count stays constant, to obtain a number of constant periods (Ncp), and to compare the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit);
and
a frequency shifter (FSH) arranged to trigger said oscillator to shift the master clock frequency whenever the number count monitor (NCM) has determined that the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).

9 more elements

A method of generating a sample clock signal (SCLK) from an input signal (FD), the method comprising:

generating a master clock (MOSC) with a master clock period;
generating a synchronization pulse (FD_OSC) from detecting a start of an input signal period (FD_PER) of the input signal (FD) and, upon detecting the start, generating the synchronization pulse (FD_OSC) in synchronization with the master clock (MOSC);
counting master clock periods between subsequent synchronization pulses to obtain the number of the master clock periods between the subsequent synchronization pulses as a number count;
determining a number of trim periods from multiplying the number count with a pre-determined phase shift fraction (PhPerc);
generating the sample clock signal (SLCK) with a clock signal period (SCLK_PER) as an in-phase sample clock corresponding to the number count (CNT) and with a delay relative to the synchronization pulse corresponding to the number of trim periods (TRM);
determining during how many input signal periods the number count stays constant, to obtain a number of constant periods (Ncp);
comparing the number of constant periods (Ncp) with a critical number of constant periods (Ncp_crit);
and
shifting the master clock frequency whenever the number of constant periods (Ncp) exceeds the critical number of constant periods (Ncp_crit).

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/035,869Filed 22 Nov 2013
Published: US 2016/0290804 A16 Oct 2016
Granted: 6 Nov 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

G01C 19/5726
Using planar vibrating masses driven in a translation vibration along an axis: signal processing
G01C 19/04
Rotary gyroscopes: details
G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
G06F 1/1694
Constructional details or arrangements related to integrated I/O peripherals not covered by groups G06F1/1635 - G06F1/1675: the I/O peripheral…

Family

US 2016/0290804 A1Pre-grant publication · published 6 Oct 2016
US 10,119,822 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key