Printing element substrate, printhead, and printing apparatus

A printhead comprising:

• a plurality of printing element substrates,
• wherein each printing element substrate includes
• a printing element,
• a driving circuit configured to drive the printing element,
• a receiver circuit configured to receive a first signal and a second signal, and
• a correction circuit configured to correct a phase difference between the first signal and the second signal received by the receiver circuit, and output the corrected first and second signals to the driving circuit,
• the correction circuit includes
• a first delay circuit configured to generate a plurality of first delayed signals having different delay times with respect to the first signal, and
• a second delay circuit configured to generate a plurality of second delayed signals having different delay times with respect to the second signal,
• the correction circuit specifies a phase of the corrected first signal to be output to the driving circuit, on the basis of comparison between the plurality of first delayed signals and the second signal, and
• the correction circuit specifies a phase of the corrected second signal to be output to the driving circuit, on the basis of comparison between the plurality of second delayed signals and the corrected first signal having the specified phase.

A printing apparatus comprising:

• a printhead including a plurality of printing element substrates,
• wherein each printing element substrate includes
• a printing element,
• a driving circuit configured to drive the printing element,
• a receiver circuit configured to receive a first signal and a second signal, and
• a correction circuit configured to correct a phase difference between the first signal and the second signal received by the receiver circuit, and output the corrected first and second signals to the driving circuit,
• the correction circuit includes
• a first delay circuit configured to generate a plurality of first delayed signals having different delay times with respect to the first signal, and
• a second delay circuit configured to generate a plurality of second delayed signals having different delay times with respect to the second signal,
• the correction circuit specifies a phase of the corrected first signal to be output to the driving circuit, on the basis of comparison between the plurality of first delayed signals and the second signal, and
• the correction circuit specifies a phase of the corrected second signal to be output to the driving circuit, on the basis of comparison between the plurality of second delayed signals and the corrected first signal having the specified phase.