Nonvolatile memory cell with improved isolation structures
AssigneeWafertech, LLC
InventorSwen Wang
Life of this patent
Estimating the term…
Abstract
A method for forming a non-volatile memory cell is provided. The method comprises: forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration; forming a plurality of spaced apart higher concentration regions with the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration; and forming a plurality of floating gate transistors in the field region between the higher concentration regions.
Claims21
A method for forming a non-volatile memory cell, comprising:
- forming a field region with a first impurity type in a semiconductor substrate, the field region having a first impurity concentration;
- forming a plurality of spaced apart higher concentration regions comprising the first impurity type within the field region, the higher concentration regions each having a higher concentration than the first impurity concentration;
- and
- forming a plurality of floating gate transistors in the field region between the higher concentration regions, wherein two respective adjacent ones of the plurality of floating gate transistors are isolated from each other by a respective one of the plurality of higher concentration regions, and wherein the non-volatile memory cell is free of shallow trench isolation (STI).
A method for forming a non-volatile memory cell, comprising:
- providing a substrate region;
- forming spaced apart heavier doped impurity regions of a first impurity type in the substrate region;
- forming lesser doped impurity regions of the first impurity type in the substrate region;
- and
- forming a plurality of floating gate transistors in the lesser doped impurity regions, wherein two respective adjacent ones of the plurality of floating gate transistors are isolated from each other by a respective one of the heavier doped impurity regions, and wherein the non-volatile memory cell is free of shallow trench isolation (STI).
A method for forming a non-volatile memory cell, comprising:
- forming a P-field region in a semiconductor substrate, the P-field region having a first impurity concentration;
- forming a plurality of spaced apart higher concentration P+ regions within the P-field region, the higher concentration P+ regions each having a higher concentration than the first impurity concentration;
- and
- forming a plurality of floating gate transistors in the P-field region between the higher concentration P+ regions, wherein two respective adjacent ones of the plurality of floating gate transistors are isolated from each other by a respective one of the plurality of higher concentration P+ regions, and wherein the non-volatile memory cell is free of shallow trench isolation (STI).
Dependencies are inferred from the claim text.