US 10,096,631 B2Granted

Signal processing circuit and semiconductor device including the signal processing circuit

AssigneeSemiconductor Energy Laboratory Co., Ltd.

InventorTakahiko Ishizu

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Abstract

Provided is a semiconductor device that can operate stably. All transistors included in the semiconductor device are transistors each of which contains an oxide semiconductor in a channel formation region. The transistor includes a front gate and a back gate. The threshold voltage of the transistor can be shifted in the positive direction or the negative direction depending on a potential applied to the back gate. To make the transistor in a conducting state, the threshold voltage is shifted in the negative direction to increase the amount of current flowing in the transistor, and to make the transistor in a non-conducting state, the threshold voltage is shifted in the positive direction to decrease the amount of current flowing in the transistor. A circuit of the semiconductor device that utilizes this effect and includes transistors all having the same polarity is formed.

Claims22

Dependent claims

A signal processing circuit comprising:

a first circuit;
a second circuit;
a first wiring;
a second wiring;
a third wiring;
a fourth wiring;
a fifth wiring;
and
a sixth wiring,
wherein the first circuit comprises a first terminal, a second terminal, a third terminal, a first transistor, and a second transistor,
wherein the second circuit comprises a fourth terminal, a fifth terminal, a sixth terminal, a third transistor, and a fourth transistor,
wherein each of the first transistor, the second transistor, the third transistor, and the fourth transistor comprises a first gate and a second gate,
wherein one of a source and a drain of the first transistor is electrically connected to the first terminal,
wherein one of a source and a drain of the second transistor is electrically connected to the second terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to the third terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the third terminal,
wherein the first gate of the first transistor is electrically connected to the first wiring,
wherein the first gate of the second transistor is electrically connected to the second wiring,
wherein the second gate of the first transistor is electrically connected to the third wiring,
wherein the second gate of the second transistor is electrically connected to the fourth wiring,
wherein one of a source and a drain of the third transistor is electrically connected to the fourth terminal,
wherein one of a source and a drain of the fourth transistor is electrically connected to the fifth terminal,
wherein the other of the source and the drain of the third transistor is electrically connected to the sixth terminal,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the sixth terminal,
wherein the first gate of the third transistor is electrically connected to the fifth wiring,
wherein the first gate of the fourth transistor is electrically connected to the sixth wiring,
wherein the second gate of the third transistor is electrically connected to the fifth wiring,
wherein the second gate of the fourth transistor is electrically connected to the sixth wiring,
wherein the sixth terminal is electrically connected to one of the first terminal and the second terminal,
wherein an inverted signal of a signal input to the second wiring is input to the first wiring, and
wherein an inverted signal of a signal input to the sixth wiring is input to the fifth wiring.

28 more elements

A signal processing circuit comprising:

a circuit;
a first wiring;
a second wiring;
a third wiring;
and
a fourth wiring,
wherein the circuit comprises a first terminal, a second terminal, a third terminal, a first transistor, and a second transistor,
wherein each of the first transistor and the second transistor comprises a first gate and a second gate,
wherein one of a source and a drain of the first transistor is electrically connected to the first terminal,
wherein one of a source and a drain of the second transistor is electrically connected to the second terminal,
wherein the other of the source and the drain of the first transistor is electrically connected to the third terminal,
wherein the other of the source and the drain of the second transistor is electrically connected to the third terminal,
wherein the first gate of the first transistor is electrically connected to the first wiring,
wherein the first gate of the second transistor is electrically connected to the second wiring,
wherein the second gate of the first transistor is electrically connected to the third wiring,
wherein the second gate of the second transistor is electrically connected to the fourth wiring,
wherein an inverted signal of a signal input to the second wiring is input to the first wiring,
wherein a potential for changing a threshold voltage of the first transistor is applied to the third wiring, and
wherein a potential for changing a threshold voltage of the second transistor is applied to the fourth wiring.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/363,148Filed 29 Nov 2016
Priority: JP 2015-23314730 Nov 2015
Published: US 2017/0154909 A11 Jun 2017
Granted: 9 Oct 2018
Term ends: Not estimatedThe source records don’t support an estimate.

Classification32 codes

H10F 39/8037
Pixels having integrated switching, control, storage or amplification elements: the integrated elements comprising a transistor
G09G 3/20
Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes: for presentation of an…
G09G 3/2092
For presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged…:…
G09G 3/3225
Organic, e.g. using organic light-emitting diodes [OLED]: using an active matrix