Folded divider architecture
AssigneeSTMicroelectronics Asia Pacific Pte Ltd
InventorBeng-Heng Goh
Life of this patent
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Abstract
A circuit includes a counter circuit, a logic circuit, and a clock divider. The counter circuit includes a clock divider counter to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal. The logic circuit compares a value contained in the divider counter to a reference value and generates an end count signal as a function of the value contained in the divider counter matching the reference value, and transitions a toggle signal at a same edge of each pulse of the end count signal. The clock divider counter is reloaded with the most significant bits of the divider value as a function of the end count signal. The clock divider generates a divided version of the clock signal as a function of the toggle signal.
Claims16
A circuit, comprising:
- a counter circuit comprising:
- a clock divider counter configured to be loaded with most significant bits of a divider value, and decremented at a same edge of each pulse of a clock signal,
- logic configured to:
- compare a value contained in the divider counter to a reference value, and generate an end count signal as a function of the value contained in the divider counter matching the reference value,
- wherein the reference value is set to zero as a function of a least significant bit of the divider value and assertion of a toggle signal,
- wherein the reference value is also set to zero as a function of the least significant bit of the divider value, deassertion of the toggle signal, and assertion of a second toggle signal;
- wherein the clock divider counter is also configured to be reloaded with the most significant bits of the divider value as a function of the end count signal;
- and
- a clock divider configured to:
- transition a first toggle signal at a same edge of each pulse of the end count signal,
- transition a second toggle signal at a same edge of every other pulse of the end count signal, and
- generate a divided version of the clock signal as a function of the first and second toggle signals.
A method, comprising:
- loading a clock divider counter with most significant bits of a divider value;
- decrementing the clock divider counter at a same edge of each pulse of a clock signal;
- comparing a value contained in the divider counter to a reference value and generate an end count signal as a function of the value contained in the divider counter matching the reference value, using logic circuitry;
- wherein the divider value is even, the reference value is set to 1;
- wherein the divider value is odd, the reference value is set to 1, except for every other assertion of the end count signal where the divider value is set to 0;
- transitioning a toggle signal at a same edge of each pulse of the end count signal,
- reloading the clock divider counter with the most significant bits of the divider value as a function of the end count signal;
- and
- generating a divided version of the clock signal as a function of the toggle signal, using the clock divider.
Dependencies are inferred from the claim text.