Analog front end circuit of an optical pulse energy digitizer
AssigneeRockwell Collins, Inc.
InventorHan Chi Hsieh
Life of this patent
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Abstract
An analog front end circuit of an optical pulse energy digitizer includes a multiphase clock circuit, a demultiplexer configured to demultiplex a current pulse stream into demultiplexed current pulse streams, and integrate-and-dump circuits coupled with the demultiplexer. Each ingrate and dump circuit is configured to convert one of the demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream. The multiphase clock circuit includes latches having outputs coupled to a combination logic circuit. The combination logic circuit is configured to provide clock signals for the integrate-and-dump circuits.
Claims14
An analog front end circuit of an optical pulse energy digitizer, the analog front end circuit comprising:
- a demultiplexer configured to demultiplex a current pulse stream into a plurality of demultiplexed current pulse streams;
- a plurality of integrate-and-dump circuits coupled to the demultiplexer, each of the plurality of the integrate-and-dump circuits being configured to convert one of the plurality of demultiplexed current pulse streams to provide a demultiplexed voltage pulse stream;
- and
- a multiphase clock circuit comprising a plurality of latches having outputs coupled to a combination logic circuit, the combination logic circuit being configured to provide a plurality of clock signals for the plurality of integrate-and-dump circuits, wherein each of the clock signals is a respective clock signal for a respective integrate-and-dump circuit of the integrate-and-dump circuits.
A method of conditioning signals in an analog front end circuit of an optical pulse energy digitizer, the method comprising:
- demultiplexing a current mode pulse stream into N demultiplexed current mode pulse streams using a demultiplexer, where N is an integer;
- and
- converting each of the demultiplexed current mode pulse streams to each of a plurality of respective voltage mode pulse streams using a set of N integrate-and-dump circuits, wherein the demultiplexer and the set of the integrate-and-dump circuits are clocked by N clock signals, the N clock signals being provided by a multiphase clock circuit comprising a set of N latches having N outputs coupled to a combination logic circuit, the combination logic circuit being configured to provide the N clock signals.
Dependencies are inferred from the claim text.