Electrostatic discharge protection using a guard region
AssigneeNXP B.V.
InventorDa-Wei Lai
Life of this patent
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Abstract
A silicon controlled rectifier (SCR) circuit is configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage. The SCR circuit includes a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector. A second bipolar NPN transistor has a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and an emitter electrically connected to the reference voltage. A guard region is configured and arranged to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.
Claims19
An apparatus comprising:
- a silicon controlled rectifier (SCR) circuit configured to shunt electrostatic discharge (ESD) current from a node to a reference voltage, the SCR circuit including:
- a first bipolar PNP transistor having a first emitter connected to the node, a first base, and a first collector;
- a second bipolar NPN transistor having a second collector sharing a first region with the first base, a second base sharing a second region with the first collector, and a second emitter electrically connected to the reference voltage, wherein the first region comprises a first N-well;
- and
- a guard region arranged between the first emitter and the second emitter, wherein the guard region comprises a second N-well separate and distinct from the first N-well, the guard region is tied to both the first collector and the second base such that the guard region is at a same voltage as the first collector and the second base, and the guard region is configured to delay triggering of the SCR circuit in response to an ESD event by impeding current flow in the second region.
A method for providing electrostatic discharge (ESD) protection using a silicon controlled rectifier (SCR) circuit, the method comprising:
- charging, in response to an ESD event, a resistor-capacitor (RC) trigger circuit;
- enabling, in response to charge on the RC trigger circuit, a first bipolar transistor in the SCR circuit;
- delaying enabling of a second bipolar transistor of the SCR circuit by impeding current through a region corresponding to a collector of the first bipolar transistor, which is shared by a base of the second bipolar transistor, using a guard region that comprises a first N-well, wherein
- the first N-well is separate and distinct from a second N-well that is shared by a base of the first bipolar transistor and a collector of the second bipolar transistor, and
- the guard region is tied to the collector of the first bipolar transistor and the base of the second bipolar transistor such that the guard region is at a same voltage as the collector of the first bipolar transistor and the base of the second bipolar transistor;
- and
- shunting, subsequent to the delaying, ESD current through the first and second bipolar transistors of the SCR circuit.
Dependencies are inferred from the claim text.