PCB hybrid redistribution layer
AssigneeMultek Technologies Limited
InventorsJoan K. Vrtis, Michael James Glickman, Todd Robinson, Hollese Galyon
Life of this patent
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Abstract
A hybrid PCB system has a hybrid redistribution layer that redistributes a large pad-to-pad pitch to a smaller, finer pad-to-pad pitch and applies hybrid materials to balance the thermal-mechanical stress. The hybrid PCB system combines wafer level packaging, IC substrate and high density PCB technologies within a single hybrid PCB. The hybrid PCB system addresses the opportunity for interconnect reliability, design and assembly of a electronic components with pad pitches less than 400 microns directly to a PCB without need of an IC substrate or interposer.
Claims22
A printed circuit board comprising:
- a. an inner core structure comprising a laminated stack of a plurality of non-conductive layers and a plurality of conductive layers, wherein the plurality of non-conductive layers have a first coefficient of thermal expansion value and a first elastic modulus value;
- b. a buffer layer laminated to the inner core structure, wherein the buffer layer comprises a first dielectric material having a second coefficient of thermal expansion value less than the first coefficient of thermal expansion value, further wherein the buffer layer has a second elastic modulus value;
- c. an intermediate conductive layer coupled to the buffer layer;
- d. an outer layer coupled to the intermediate conductive layer and the buffer layer, wherein the outer layer comprises a second dielectric material having a third coefficient of expansion value less than the second coefficient of thermal expansion value, further wherein the outer layer has a third elastic modulus value, wherein the second elastic modulus value is less than the first elastic modulus value and the second elastic modulus value is less than the third elastic modulus value;
- and
- e. an outer conductive layer coupled to the outer layer.
A printed circuit board comprising:
- a. an inner core structure comprising a laminated stack of a plurality of non-conductive layers and a plurality of conductive layers including an inner core structure outer surface conductive layer, wherein the inner core structure outer surface includes a plurality of inner core structure circuit features each having corresponding inner core structure circuit feature dimensions, further wherein each of the plurality of the inner core structure circuit features comprise one of a first contact pad diameter, a first trace transmission line width, or a first via end diameter, wherein the plurality of non-conductive layers have a first coefficient of thermal expansion value;
- b. an outer layer coupled to the inner core structure, wherein the outer layer comprises a dielectric material having a second coefficient of expansion value less than the first coefficient of thermal expansion value;
- and
- c. an outer conductive layer coupled to the outer layer, wherein the outer conductive layer includes a plurality of outer layer circuit features each having corresponding outer surface circuit feature dimensions, further wherein each of the plurality of the outer layer circuit features comprise one of a second contact pad diameter, a second trace transmission line width, or a second via end diameter, wherein the outer surface circuit feature dimensions are smaller than the inner core structure circuit feature dimensions.
Dependencies are inferred from the claim text.