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US RE51,079 E1Granted
Source/drain contacts for non-planar transistors
AssigneeIntel Corporation
InventorsSameer S. Pradhan, Subhash M. Joshi, Jin-Sung Chun
Life of this patent
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Abstract
The present description relates to the field of fabricating microelectronic devices having non-planar transistors. Embodiments of the present description relate to the formation of source/drain contacts within non-planar transistors, wherein a titanium-containing contact interface may be used in the formation of the source/drain contact with a discreet titanium silicide formed between the titanium-containing interface and a silicon-containing source/drain structure.
Claims20
A microelectronic device, comprising:
- a substrate;
- a transistor on the substrate comprising a pair of gate spacers, a gate dielectric layer between the pair of gate spacers and adjacent the substrate, a gate electrode between the pair of gate spacers and adjacent the gate dielectric, and a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode;
- a dielectric material on the substrate and the transistor;
- a source region in the substrate;
- a drain region in the substrate;
- a source contact extending through the dielectric material, wherein the source contact is adjacent the source region;
- a drain contact extending through the dielectric material, wherein the drain contact is adjacent the drain region;
- wherein at least one of the source contact and the drain contact comprises an interface adjacent its respective source region or drain region, a contact interface layer adjacent the interface, and a conductive contact material adjacent the contact interface layer;
- and
- wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure.
7 more elements
A method of fabricating a microelectronic device, comprising:
- forming a substrate;
- forming a transistor on the substrate comprising:
- forming a pair of gate spacers, forming a gate dielectric layer between the pair of gate spacers and adjacent the substrate;
- forming a gate electrode between the pair of gate spacers and adjacent the gate dielectric;
- and
- forming a capping dielectric layer between the pair of gate spacer and adjacent the gate electrode;
- forming a source region in the substrate;
- forming a drain region in the substrate;
- forming a dielectric material on the substrate and the transistor;
- forming a contact opening through the dielectric material to expose a portion of one of the source region and the drain region;
- forming an interface adjacent the portion of one of the source region and the drain region;
- forming contact interface layer adjacent the interface, wherein the contact interface layer abuts at least one of a portion of one gate spacer and at least a portion of the capping structure;
- and
- forming a conductive contact material adjacent the contact interface layer.
11 more elements
Dependencies are inferred from the claim text.