Memory system having high data transfer efficiency and host controller

A method for transferring data between a memory device and a system memory executed by a host controller, the system memory storing first, third, and fourth descriptors, the method comprising:

• (1) loading the first descriptor including a plurality of pointers with attributes;
• (2) acquiring a pointer from the loaded first descriptor, wherein the pointer indicates a leading region of the third descriptor;
• (3) loading the third descriptor based on the pointer to issue a command, wherein the third descriptor includes command issue information and attributes;
• (4) issuing a command according to the loaded third descriptor;
• (5) loading the fourth descriptor based on the pointer, wherein the fourth descriptor includes a number of DMA execution information and attributes;
• (6) when the issued command is a read-command, reading data from the system memory to a data buffer in accordance with the fourth descriptor and transferring the data from the data buffer to the memory device in accordance with the third descriptor;
• when the issued command is a write-command, reading data from the memory device to the data buffer in accordance with the third descriptor, and transferring the data from the data buffer to the system memory in accordance with the fourth descriptor;
• (7) repeating (2) to (6) until an attribute of the first descriptor indicates the end of descriptor;
• and
• (8) generating an interrupt when a data transfer is end or during a DMA data transfer,
• wherein the third descriptor includes information to generate a data transfer command of the memory device, a command argument, a command number, a block length, and the number of blocks,
• wherein the fourth descriptor includes information to designate system memory areas addresses, and sizes for each of a plurality of scattered data in the system memory.

A DMA transfer control method comprising:

• loading, from a memory, a second descriptor pointer described first among a plurality of second descriptor pointers described in a first descriptor, the first descriptor including a set of a plurality of pointers indicating a plurality of second descriptors;
• loading, from the memory a second descriptor indicated by the loaded second descriptor pointer;
• loading, from the memory, a third descriptor described at a head of the second descriptor, writing contents of the third descriptor in a register, and issuing a command, the third descriptor including information for issuing an SD command;
• loading a fourth descriptor from the memory, loading data indicated by an address described in the fourth descriptor, and transferring the data between a system memory and a buffer, the fourth descriptor including information indicating addresses and sizes of a plurality of data arranged in the system memory, the fourth descriptor being a pair with the third descriptor;
• and
• repeating the above-mentioned operation, and generating an interrupt when all the data has been transferred.