Apparatus and circuit for processing carrier aggregation

An apparatus for supporting carrier aggregation, the apparatus comprising:

• a first component carrier (CC) circuit configured to estimate a first frequency offset for a first CC to be processed by the first CC circuit;
• a second CC circuit configured to estimate a second frequency offset for a second CC to be processed by the second CC circuit;
• a reference clock generator configured to generate a reference clock using the first frequency offset or the second frequency offset;
• and
• a phase lock loop (PLL) circuit configured to generate a reception carrier frequency or a transmission carrier frequency for the first CC or the second CC.

An apparatus for supporting carrier aggregation, the apparatus comprising:

• a first component carrier (CC) circuit configured to:
• estimate a first frequency offset for a first CC to be processed by the first CC circuit, and
• compensate the estimated first frequency offset;
• a second CC circuit configured to:
• estimate a second frequency offset for a second CC to be processed by the second CC circuit, and
• compensate the estimated second frequency offset;
• a reference clock generator configured to generate a reference clock using the first frequency offset or the second frequency offset;
• and
• a phase lock loop (PLL) circuit configured to generate a reception carrier frequency or a transmission carrier frequency for the first CC or the second CC.

An apparatus for supporting carrier aggregation, the apparatus comprising:

• a reference clock generator configured to generate a reference clock;
• a plurality of phase lock loop (PLL) circuits configured to generate a plurality of carrier frequencies that respectively correspond to a plurality of component carriers (CCs), using the reference clock generated by the reference clock generator;
• and
• a plurality of CC circuits configured to estimate a plurality of frequency offsets that respectively correspond to the plurality of CCs, using the plurality of generated carrier frequencies by the plurality of PLL circuits.

An apparatus for supporting carrier aggregation (CA), the apparatus comprising:

• a plurality of antennas;
• and
• at least one processor configured to
• respectively generate a plurality of carrier frequencies that respectively correspond to a plurality of component carriers (CCs), using a reference clock generated by a reference clock generator, and
• estimate a plurality of frequency offsets that respectively correspond to the plurality of CCs, using the plurality of generated carrier frequencies.

A home evolved nodeB (HeNB) for supporting carrier aggregation (CA), the HeNB comprising:

• a reference clock generator configured to generate a reference clock;
• a plurality of phase lock loop (PLL) circuits configured to generated a plurality of carrier frequencies that respectively correspond to a plurality of component carriers (CCs), using the reference clock generated by the reference clock generator;
• and
• a plurality of CC circuits configured to estimate a plurality of frequency offsets that respectively correspond to the plurality of CCs, using the plurality of generated carrier frequencies by the plurality of PLL circuits,
• wherein each of the plurality of CC circuits includes a plurality of antennas configured to receive a carrier frequency.