Memory module, error correction method of memory controller controlling the same, and computing system including the same

A memory module comprising:

• a first sub-channel;
• a second sub-channel;
• and
• a driver circuit configured to receive a clock signal, first and second commands, and an address from a memory controller and to transmit the clock signal, the first command, and the address to the first sub-channel and transmit the clock signal, the second command, and the address to the second sub-channel,
• wherein each of the first and second sub-channels comprises:
• a plurality of first memory chips configured to store data, each first memory chip having a first input/output width;
• and
• a second memory chip configured to store an error correction code for correcting an error in the data, the second memory chip having a second input/output width, less than the first input/output width, and
• an address depth of each of the first memory chips and an address depth of the second memory chip are different from each other.

An apparatus comprising:

• a master die;
• a slave die including a memory cell array;
• a plurality of through-silicon vias electrically coupling the master die to the slave die, and configured to communicate with data between the master die and the slave die, the data being written in the memory cell array;
• error correction code (ECC) input/output lanes through which a parity for error correction is communicated, the ECC input/output lanes being separate from the plurality of through-silicon vias;
• and
• an ECC circuit configured to perform an error correction operation on the data,
• wherein the ECC circuit uses a Cyclical Redundancy Code (CRC) Check to detect errors and correct the detected errors.

A memory device comprising:

• a stack of memory dies including a plurality of slave dies and a master die, each of the plurality of slave dies including a memory cell array;
• a controller operably coupled to the master die and the plurality of slave dies;
• an error correction code (ECC) circuit configured to perform a first error correction operation on first data in a first mode, and to perform a second error correction operation on second data in a second mode;
• a plurality of through-silicon vias electrically coupling the master die to the plurality of slave dies, and configured to communicate with data between the master die and the plurality of slave dies, the data being written in the memory cell array;
• and
• ECG input/output lanes through which a parity for error correction is communicated, the ECC input/output lanes being separate from the plurality of through-silicon vias.