# US RE50,874 E1 · Memory arrays > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US RE50,874 E1 - Document ID: USRE50874E1 - Status: Granted - Kind: E1 - Application number: 18/243,035 - Filed: 2023-09-06 - Granted: 2026-04-21 - Earliest claimed: 2017-05-08 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Martin C. Roberts; Sanh D. Tang; Fred D. Fishburn - Web page: https://patentgrep.com/patent/USRE50874E1 ## CPC - H10B 12/30: {DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells} - H01L 23/528 - H10B 12/03: {Making the capacitor or connections thereto} - H10B 12/05: {Making the transistor} - H10B 12/48: {Data lines or contacts therefor} - H10B 12/50: {Peripheral circuit region structures} - H10B 53/10: characterised by the top-view layout - H10B 53/20: characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels - H10B 53/30: characterised by the memory core region - H10D 1/692: {Electrodes} - H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)} - H10D 62/235: {of IGFETs (IGFETs having buried channels H10D30/637)} - H10D 64/518: {characterised by their lengths or sectional shapes} - H01L 21/02164 - H01L 21/0217 - H01L 21/02532 - H01L 21/02595 - H01L 21/28035 - H01L 21/30604 - H01L 21/31111 - H01L 21/32134 - H10D 88/00: Three-dimensional [3D] integrated devices - H10B: ELECTRONIC MEMORY DEVICES - H01L - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually include a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. At least a portion of the channel region is horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions. The memory cells individually include a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode is electrically coupled to the first source/drain region. The second capacitor electrodes of multiple of the capacitors in the array are electrically coupled with one another. A sense-line structure extends elevationally through the vertically-alternating tiers. Individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending sense-line structure. Additional embodiments are disclosed. ## Claims ### Claim 1 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another; and a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure. ### Claim 2 (depends on 1) The array of claim 1 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through. ### Claim 3 (depends on 1) The array of claim 1 wherein the first electrode is directly electrically coupled to the first source/drain region. ### Claim 4 (depends on 1) The array of claim 1 wherein the individual second source/drain regions are directly electrically coupled to the elevationally-extending sense-line structure. ### Claim 5 (depends on 1) The array of claim 1 wherein the sense-line structure is directly electrically coupled to a horizontal longitudinally-elongated sense line that is above or below the vertically-alternating tiers. ### Claim 6 (depends on 1) The array of claim 1 wherein the second capacitor electrodes of the multiple capacitors are directly electrically coupled with one another. ### Claim 7 (depends on 6) The array of claim 6 comprising an elevationally-extending wall that is longitudinally-elongated horizontally and that directly electrically couples the second capacitor electrodes of the multiple capacitors with one another. ### Claim 8 (depends on 1) The array of claim 1 wherein the second electrode is both directly above and directly below the first electrode in a straight-line vertical cross-section. ### Claim 9 (depends on 1) The array of claim 1 wherein the second electrode is not both directly above and directly below the first electrode in any straight-line vertical cross-section. ### Claim 10 (depends on 1) The array of claim 1 wherein the first electrode is both directly above and directly below the second electrode in a straight-line vertical cross-section. ### Claim 11 (depends on 1) The array of claim 1 wherein the channel-region comprises two channel-region segments spaced elevationally apart relative one another in a straight-line vertical cross-section. ### Claim 12 (depends on 11) The array of claim 11 wherein the two channel-region segments are directly electrically coupled to one another. ### Claim 13 (depends on 12) The array of claim 12 wherein the two channel-region segments are directly electrically coupled to one another by the first source/drain region. ### Claim 14 (depends on 1) The array of claim 1 wherein individual of the tiers of memory cells comprise two of the memory cells one of which is directly above the other in that individual tier of memory cells. ### Claim 15 (depends on 1) The array of claim 1 wherein individual of the memory cell tiers have no two of the memory cells that are directly above and directly below one another in that individual memory cell tier. ### Claim 16 (depends on 1) The array of claim 1 wherein individual of the tiers of memory cells comprise the gate and another gate, one of the gate and the another gate being directly above the other in that individual tier of memory cells. ### Claim 17 (depends on 1) The array of claim 1 wherein the channel region comprises an annulus in a straight-line horizontal cross-section. ### Claim 18 (depends on 1) The array of claim 1 wherein the first source/drain region comprises an annulus in a straight-line horizontal cross-section. ### Claim 19 (depends on 1) The array of claim 1 wherein the second source/drain region comprises an annulus in a straight-line horizontal cross-section. ### Claim 20 (depends on 1) The array of claim 1 wherein the first electrode comprises an annulus in a straight-line horizontal cross-section. ### Claim 21 (depends on 1) The array of claim 1 wherein the second electrode comprises an annulus in a straight-line horizontal cross-section. ### Claim 22 (depends on 1) The array of claim 1 wherein the gate comprises an annulus in a straight-line horizontal cross-section. ### Claim 23 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure; and a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors. ### Claim 24 (depends on 23) The array of claim 23 wherein the capacitor-electrode structure is directly electrically coupled to a horizontally-elongated capacitor-electrode construction that is above or below the vertically-alternating tiers. ### Claim 25 (depends on 23) The array of claim 23 wherein the capacitor-electrode structure comprises an elevationally-extending wall that is longitudinally-elongated horizontally and that directly electrically couples the individual second capacitor together. ### Claim 26 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; a sense-line structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending sense-line structure; and a capacitor-electrode structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the elevationally-extending capacitor-electrode structure. ### Claim 27 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another; a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers; and individual of the tiers of memory cells comprising two of the memory cells one of which is directly above the other in that individual tier of memory cells. ### Claim 28 (depends on 27) The array of claim 27 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through. ### Claim 29 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow in the portion between the first and second source/drain regions; and a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region, the second capacitor electrodes of multiple of the capacitors in the array being electrically coupled with one another; a sense line electrically coupled to multiple of the second source/drain regions of individual of the transistors that are in different memory cell tiers; and individual of the tiers of memory cells comprising the gate and another gate, one of the gate and the another gate being directly above the other in that individual tier of memory cells. ### Claim 30 (depends on 29) The array of claim 29 wherein the gate and the another gate are directly electrically coupled to one another. ### Claim 31 (depends on 29) The array of claim 29 wherein the gate and the another gate are not directly electrically coupled to one another. ### Claim 32 (depends on 29) The array of claim 29 wherein the one of the gate and the another gate extends longitudinally directly above the capacitor in a straight-line vertical cross-section. ### Claim 33 (depends on 29) The array of claim 29 wherein the other of the gate and the another gate extends longitudinally directly under the capacitor in a straight-line vertical cross-section. ### Claim 34 (depends on 33) The array of claim 33 wherein the one of the gate and the another gate extends longitudinally directly above the capacitor in the straight-line vertical cross-section. ### Claim 35 A memory array, comprising: vertically alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second source/drain regions comprising polysilicon, the first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally oriented for horizontal current flow; and a data storage element comprising first and second electrodes having an insulator there-between; a conductive line structure extending elevationally through the vertically alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the conductive line structure; and a horizontal conductive line that is above or below the vertically alternating tiers, the conductive line structure being directly electrically coupled to the horizontal line. ### Claim 36 A method of forming a memory array, comprising: forming a plurality of insulative tiers; forming a plurality of memory cell tiers, the memory cell tiers vertically alternating with the insulative tiers, the forming the memory cell tiers comprising: forming a transistor comprising first and second polysilicon-comprising source/drain regions having a channel region there-between at least a portion of the channel region being horizontally-oriented for horizontal current flow; forming a gate operatively proximate the channel region; and forming a data storage element comprising first and second electrodes having an insulator there-between; and forming a conductive line structure extending elevationally through the plurality of insulative tiers and the plurality of memory cell tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the elevationally-extending conductive line structure. ### Claim 37 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second polysilicon-comprising source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow; and a data storage element comprising first and second electrodes having an insulator there-between, the first electrode being electrically coupled to the first source/drain region; and a conductive line structure extending elevationally through the vertically-alternating tiers. ### Claim 38 (depends on 37) The array of claim 37 wherein all of the channel region is horizontally-oriented for horizontal current flow there-through. ### Claim 39 (depends on 37) The array of claim 37 wherein individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers are electrically coupled to the elevationally-extending conductive line structure. ### Claim 40 (depends on 37) The array of claim 37 wherein the second electrodes of the multiple data storage elements are directly electrically coupled with one another. ### Claim 41 (depends on 37) The array of claim 37 wherein the channel-region comprises two channel-region segments spaced elevationally apart relative one another in a straight-line vertical cross-section. ### Claim 42 (depends on 37) The array of claim 37 wherein the channel region comprises an annulus in a straight-line horizontal cross-section. ### Claim 43 A memory array, comprising: vertically-alternating tiers of insulative material and memory cells, the memory cells individually comprising: a transistor comprising first and second polysilicon-comprising source/drain regions having a channel region there-between and a gate operatively proximate the channel region, at least a portion of the channel region being horizontally-oriented for horizontal current flow; and a capacitor comprising first and second electrodes having a capacitor insulator there-between, the first electrode being electrically coupled to the first source/drain region; a first conductive structure extending elevationally through the vertically-alternating tiers, individual of the second source/drain regions of individual of the transistors that are in different memory cell tiers being electrically coupled to the first conductive structure; and a second conductive structure extending elevationally through the vertically-alternating tiers, individual of the second electrodes of individual of the capacitors that are in different memory cell tiers being electrically coupled to the second conductive structure.