Input receiver circuits selectively connected to input/output pad based on operation mode

An input/output interface for a memory device comprising:

• a mode selection circuit configured to generate a mode selection signal;
• a termination circuit configured to provide the input/output interface with one of a VSSQ termination, a VDDQ termination and a termination off mode in response to the mode selection signal;
• and
• an output driver block configured to transmit a data output signal, the output driver block being connected to an input/output pad and comprising a plurality of output driver circuits, wherein one of the plurality of output driver circuits is configured to selectively operate according to the mode selection signal, the mode selection signal indicating a termination type of the termination circuit,
• wherein each of the plurality of output driver circuits has different topology suitable for different operation speed, the operation speed selected from a group including a low speed operation, and a high speed operation faster than the low speed operation.

An input/output interface circuit for a memory device comprising:

• a mode selection circuit configured to generate a mode selection signal;
• a termination circuit configured to provide the input/output interface with one of a VSSQ termination, a VDDQ termination and a termination off mode in response to the mode selection signal;
• and
• an output driver block connected to an input/output pad including,
• a first output driver circuit configured to transmit a output data signal, the first output driver circuit including a NMOS pull-up driver;
• and
• a second output driver circuit configured to transmit the output data signal, the second output driver circuit including a PMOS pull-up driver,
• wherein one of the first output driver circuit and the second output driver circuit is selected to transmit the output data signal in response to the mode selection signal.

An input/output interface circuit for a dynamic random access memory (DRAM) device, the input/output interface circuit comprising:

• a mode register configured to store an operation mode of the DRAM device, the operation mode indicating one of high speed operation mode and low speed operation mode;
• an input receiver block connected with an input/output pad, the input receiver block including a first input receiver circuit and a second input receiver circuit, and one of the first input receiver circuit and the second input receiver circuit being selectively connected to the input/output pad based on a mode selection signal corresponding to the operation mode and receiving an input data signal, and wherein the first input receiver circuit and the second input receiver circuit have different structures configured for different operation speeds;
• and
• an on-die-termination (ODT) circuit connected between the input/output pad and a circuit ground, and selectively turned on or turned off according to the operation mode,
• wherein, when the operation mode indicates high speed operation mode, the first input receiver circuit is connected to the input/output pad and receives the input data signal while the ODT circuit is turned on, and when the operation mode indicates low speed operation mode, the second input receiver circuit is connected to the input/output pad and receives the input data signal while the ODT circuit is turned off.

A memory system comprising:

• a memory device including a first internal circuit and a first input/output (I/O) interface, wherein the first internal circuit includes a mode register configured to store an operation mode of the memory device, the operation mode being one of high speed operation mode or low speed operation mode, wherein the first I/O interface includes:
• a first input receiver block connected with a first input/output pad, the first input receiver block including a first input receiver circuit and a second input receiver circuit, one of the first input receiver circuit and the second input receiver circuit being selectively connected to the first input/output pad based on a mode selection signal corresponding to the operation mode and receiving an input data signal, wherein the first input receiver circuit and the second input receiver circuit have different structures configured for different operation speeds;
• a first output driver block connected with the first input/output pad, the first output driver block including a first output driver circuit and a second output driver circuit, one of the first output driver circuit and the second output driver circuit being selectively connected to the first input/output pad according to the operation mode and outputting an output data signal;
• and
• a first on-die-termination (ODT) circuit connected between the first input/output pad and a circuit ground;
• and
• a memory controller including a second internal circuit and a second input/output (I/O) interface, wherein the second I/O interface includes:
• a second input receiver block connected with a second input/output pad receiver block including third and fourth input receiver circuits, one of the third and fourth input receiver circuits being selectively connected to the second input/output pad and receiving the output data signal from the first output driver block;
• a second output driver block connected with the second input/output pad, the second output driver block including third and fourth output driver circuits, one of the third and fourth output driver circuits being selectively connected to the second input/output pad and driving the input data signal to the first input receiver block;
• and
• a second on-die-termination (ODT) circuit connected between the second input/output pad and the circuit ground,
• wherein, when the operation mode indicates high speed operation mode, the first input receiver circuit is connected to the input/output pad and receives the input data signal while the first ODT circuit is turned on, and when the operation mode indicates low speed operation mode, the second input receiver circuit is connected to the input/output pad and receives the input data signal while the first ODT circuit is turned off.

An input/output interface circuit for a memory controller,

• wherein the input/output interface circuit is configured to operate based on an operation mode comprising a high speed operation mode and a low speed operation mode, and
• wherein the input/ output interface circuit comprises:
• an input receiver block connected with an input/output pad, the input receiver block including a first input receiver circuit and a second input receiver circuit, and one of the first input receiver circuit and the second input receiver circuit being selectively connected to the input/output pad based on a mode selection signal corresponding to the operation mode and receiving an input data signal, wherein the first input receiver circuit and the second input receiver circuit have different structures configured for different operation speeds;
• and
• an on-die-termination (ODT) circuit connected between the input/output pad and a circuit ground, and selectively turned on or turned off according to the operation mode,
• wherein, when the operation mode indicates high speed operation mode, the first input receiver circuit is connected to the input/output pad and receives the input data signal while the ODT circuit is turned on, and when the operation mode indicates low speed operation mode, the second input receiver circuit is connected to the input/output pad and receives the input data signal while the ODT circuit is turned off.