Liquid crystal display

A liquid crystal display, comprising:

• a first substrate,
• a first gate line, a second gate line, a first data line, and a second data line, and a reference voltage line on the first substrate;
• a first thin film transistor connected to the first gate line and the first data line, and including a first gate electrode, a first source electrode, a first drain electrode, and a first semiconductor;
• a second thin film transistor connected to the second gate line and the second data line, and including a second gate electrode, a second source electrode, a second drain electrode, and a second semiconductor;
• a first pixel electrode which contacts a portion of the first drain electrode, and a second pixel electrode which contacts a portion of the second drain electrode;
• a passivation layer on the first pixel electrode, the second pixel electrode, the first thin film transistor, and the second thin film transistor;
• and
• a reference electrode on the passivation layer, and overlapping the first pixel electrode and the second pixel electrode,
• wherein the reference electrode includes a plurality of branch electrodes,
• wherein the first thin film transistor is right of the first data line, and the second thin film transistor is left of the second data line, in a plan view of the liquid crystal display,
• the first drain electrode directly contacts the first pixel electrode, and the second drain electrode directly contacts the second pixel electrode,
• wherein the first gate electrode overlaps the first semiconductor and the first data line, and
• wherein the second gate electrode overlaps the second semiconductor and the second data line.

A liquid crystal display, comprising:

• a first substrate,
• a first gate line, a second gate line, a first data line, and a second data line, and a reference voltage line on the first substrate;
• a first thin film transistor connected to the first gate line and the first data line, and including a first gate electrode, a first source electrode, a first drain electrode, and a first semiconductor;
• a second thin film transistor connected to the second gate line and the second data line, and including a second gate electrode, a second source electrode, a second drain electrode, and a second semiconductor;
• a first pixel electrode which contacts a portion of the first drain electrode, and a second pixel electrode which contacts a portion of the second drain electrode;
• a passivation layer on the first pixel electrode, the second pixel electrode, the first thin film transistor, and the second thin film transistor;
• and
• a reference electrode on the passivation layer, and overlapping the first pixel electrode and the second pixel electrode,
• wherein the reference electrode includes a plurality of branch electrodes,
• wherein the first thin film transistor between the first and second data lines is closer to the first data line than to the second data line, and the second thin film transistor between the first and second data lines is closer to the second data line than to the first data line, in a plan view of the liquid crystal display,
• wherein the first drain electrode is formed in parallel to the first data line, and the second drain electrode is formed in parallel to the second data line,
• wherein the first gate electrode overlaps the first semiconductor and the first data line and
• wherein the second gate electrode overlaps the second semiconductor and the second data line.