Semiconductor device for short-circuiting nodes connected to a word line control circuit and control method for the same

A semiconductor device comprising:

• a memory cell array including i memory cells (i is an integral number larger than 2) capable of holding data each of which includes a charge storage layer and control gate and the i memory cells are serially connected along a current path;
• and
• a voltage generator circuit which generates a first voltage and second voltage, transferring the first and second voltages to word lines connected to the control gates of the memory cells,
• wherein the voltage generator circuit
• transfers the first voltage to the word line connected to the control gate of the ith memory cell, and
• transfers the second voltage to the word lines connected to the control gates of the (i+1)th and (i+2)th memory cells which are arranged on a drain side of the ith memory cell.

A control method of a semiconductor device comprising:

• causing a first voltage generator circuit to generate a first voltage and output the first voltage to a first node;
• causing a second voltage generator circuit to generate a second voltage and output the second voltage to a second node;
• causing a controller to set a first MOS transistor in an on state and short-circuit the first node and second node;
• and
• causing the controller to control a period in which the first MOS transistor is maintained in the on state based on time.

A semiconductor device comprising:

• a memory cell array including a plurality of memory cells connected in series and each memory cell configured to store data;
• a plurality of word lines connected to gates of the memory cells, respectively;
• a word line control circuit configured to control the word lines;
• a first node connected to the word line control circuit;
• a second node connected to the word line control circuit;
• a third node connected to the word line control circuit;
• a first MOS transistor having one end connected to the first node, another end connected to the second node and a gate, the first transistor configured to equalize a voltage level of the first node and a voltage level of the second node by being turned on and short-circuiting the first node and the second node;
• a second transistor having one end connected to the second node, another end connected to the third node and a gate, the second transistor configured to equalize the voltage level of the second node and a voltage level of the third node by being turned on and short-circuiting the second node and the third node;
• and
• a controller connected to the gate of the first transistor and the gate of the second transistor and configured to perform a control operation to short circuit the first node and the second node by turning on the first MOS transistor for a first period of time, controlling a period in which the first MOS transistor is kept in an on state based on time,
• wherein
• the duration of the first period during which the first transistor is turned on to short-circuit the first node and the second node is changed,
• the voltage level of the first node is transferred to at least a first one of the word lines,
• the voltage level of the second node is transferred to at least a second one of the word lines, and
• the voltage level of the third node is transferred to at least a third one of the word lines.

A method for controlling a semiconductor device, the semiconductor device including:

• a memory cell array including a plurality of memory cells connected in series and eac memory cell configured to store data;
• a plurality of word lines connected to gates of the memory cells, respectively;
• a word line control circuit configured to control the word lines;
• a first node connected to the word line control circuit;
• a second node connected to the word line control circuit;
• a third node connected to the word line control circuit;
• a first MOS transistor having one end connected to the first node, another end connected to the second node and a gate, the first transistor configured to equalize a voltage level of the first node and a voltage level of the second node by being turned on and short-circuiting the first node and the second node:
• a second transistor having one end connected to the second node, another end connected to the third node and a gate. the second transistor configured to equalize the voltage level of the second node and a voltage level of the third node by being turned on and short-circuiting the second node and the third node,
• the method comprising:
• causing a controller to supply a control signal to set the gate of the first MOS transistor and the gate of the second transistor to thereby perform a control operation to short circuit the first node and the second node by turning on the first transistor for a first period of time and short circuit the second node and the third node by turning on the second transistor for a second period of time,
• wherein
• the duration of the first period during which the first transistor is turned on to short-circuit the first node and the second node is changed,
• the voltage level of the first node is transferred to at least a first one of the word lines,
• the voltage level of the second node is transferred to at least a second one of the word lines, and
• the voltage level of the third node is transferred to at least a third one of the word lines.