Semiconductor memory devices including error correction circuits and methods of operating the semiconductor memory devices

A memory device configured to communicate with a memory controller, the memory device comprising:

• a first storage region;
• a second storage region;
• an error correction circuit configured to correct errors with respect to first data using an error correction operation;
• an error detector configured to detect a number of error bits in the first data and output a detection signal based on a detection result;
• and
• a data output circuit configured to output corrected data that is corrected by the error correction circuit,
• wherein the error correction operation includes a first error correction operation and a second error correction operation that employs a different error correction capability from the first error correction operation,
• in response to detecting that the number of error bits in the first data stored in the first storage region does not exceed a threshold value, i) the error correction circuit is configured to read the first data from the first storage region according to the first error correction operation, and ii) the data output circuit is configured to output the first data without storing the first data in the second storage region, and
• in response to detecting that the number of error bits in the first data stored in the first storage region exceeds the threshold value, i) second data is stored in the second storage region based on the first data, ii) the error correction circuit is configured to read the second data from the second storage region according to the second error correction operation, and iii) the data output circuit is configured to output the second data.

A memory device configured to communicate with a memory controller, the memory device comprising:

• a first storage region;
• a second storage region;
• an error correction circuit configured to correct errors with respect to first data using an error correction operation;
• an error detector configured to detect a number of error bits in the first data and output a detection signal based on a detection result;
• and
• a data output circuit configured to output corrected data that is corrected by the error correction circuit,
• wherein the error correction operation includes a first error correction operation and a second error correction operation that employs a greater error correction capability from the first error correction operation,
• in response to detecting that the number of error bits in the first data stored in the first storage region does not exceed a threshold value, i) the error correction circuit is configured to read the first data from the first storage region according to the first error correction operation, and ii) the data output circuit is configured to output the first data without storing the first data in the second storage region,
• in response to detecting that the number of error bits in the first data stored in the first storage region exceeds the threshold value, i) second data is stored in the second storage region based on the first data, ii) the error correction circuit is configured to read the second data from the second storage region according to the second error correction operation, and iii) the data output circuit is configured to output the second data and
• the threshold value includes the number of error bits that is at least one error bit less than an error correction limit of the first error correction operation.

A memory device configured to communicate with a memory controller, the memory device comprising:

• a first storage region;
• a second storage region;
• an error correction circuit configured to correct errors with respect to first data using an error correction operation;
• an error detector configured to detect a number of error bits in the first data and output a detection signal based on a detection result;
• and
• a data output circuit configured to output corrected data that is corrected by the error correction circuit,
• wherein the error correction operation includes a first error correction operation having a first error correction capability and a second error correction operation having a second error correction capability that is different from the first error correction capability,
• in response to detecting that the number of error bits falls below a threshold value, i) the error correction circuit is configured to read the first data from the first storage region according to the first error correction operation, and ii) the data output circuit is configured to output the first data without storing the first data in the second storage region, and
• in response to detecting that the number of error bits exceeds the threshold value, the error correction circuit is configured to correct the errors on the first data, i) the error correction circuit is configured to read, according to the second error correction operation, second data that is stored in the second storage region based on the first data, and ii) the data output circuit is configured to output the second data.