Cross-point memory device and method for converting and storing write data and associated parity to achieve uniform bit error rates

A cross-point memory comprising:

• a memory controller configured to control a memory device including a plurality of layers forming a memory cell array, the memory controller configured to generate control signals by,
• calculating parity data from a write data according to a write request and generate a first region data including the write data and the parity data,
• converting a first address related to the write data into a plurality of second addresses related to a plurality of sub-region data classified from the first region data by converting the first address to a first physical address corresponding to the first region data, and converting the first physical address to the plurality of second addresses corresponding to the plurality of sub-region data, the plurality of second addresses for uniformizing bit error rates (BERs) among a plurality of region data, and
• generate the control signals such that based on the control signals of the memory controller, the plurality of sub-region data are distributed and stored in the plurality of layers according to the plurality of second addresses,
• wherein each region data of the plurality of region data and each sub-region data of the plurality of sub-region data are units of data for the distributing and storing of the write data and the parity data.

A method of operating a cross-point memory, the cross-point memory including a plurality of layers forming a memory cell array, the memory cell array classified into a plurality of tiles connected to respective ones of a plurality of write drivers, the method comprising:

• generating first sub-region data and second sub-region data from first region data, the first region data accompanying a first write request;
• selecting a path for transmitting the first and second sub-region data to the plurality of layers;
• and
• writing the first sub-region data to a first tile of the plurality of tiles within a first layer of the plurality of layers and writing the second sub-region data to a second tile of the plurality of tiles within a second layer of the plurality of layers such that the first region data is distributed and stored into different ones of the first tile and the second tile in different ones of the plurality of layers,
• wherein first region data and second sub-region data are units of data for the distributing and storing or reading of data, and
• wherein each tile of the plurality of tiles includes a memory cell region, a row selection unit, and a column section unit.

A method of operating a memory controller, the memory controller configured to control a write operation on memory cells disposed in a plurality of layers of a memory device, the method comprising:

• receiving, from a host, a write request and data corresponding to the write request, the write request includes a first address corresponding to region data;
• generating n pieces of sub-region data from region data by performing a first processing operation on the data;
• assigning the n pieces of region data to the plurality of layers based on an address conversion operation, the address conversion operation including converting the first address to a first physical address corresponding to the region data, and converting the first physical address to a plurality of second addresses corresponding to the n pieces of sub-region data for uniformizing bit error rates (BERs) among the plurality of region data;
• and
• controlling the write operation to write at least two of the region data in different layers according to the plurality of second addresses, wherein n is an integer equal to or larger than 2.

A cross-point memory comprising:

• a memory cell array including resistive memory cells included in a plurality of layers;
• a read/write circuit configured to perform a write operation and a read operation on the resistive memory cells;
• and
• processing circuitry configured to,
• control the write operation and the read operation on the resistive memory cells according to a received command and a received address, and
• assign data accompanying the received command to the plurality of layers,
• wherein a plurality of pieces of sub-region data to which region data corresponding to a first address is classified into that are simultaneously written to at least two layers, the region data including at least a portion of the data corresponding to the first address and parity data corresponding to the at least a portion of the data, and each of the plurality of pieces of sub-region data include a portion of the parity data,
• wherein region data and each piece of sub-region data of the plurality of pieces of sub-region data are units of data for the distributing, storing, and reading of data.