US RE50,025 E1 · Non-volatile semiconductor memory device including application of different voltages to memory cells based on their proximity to a selected memory cell

Abstract

A non-volatile semiconductor memory device has a NAND string, in which multiple memory cells are connected in series. A read procedure is performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof. In the read procedure, a first read pass voltage is applied to unselected memory cells except an adjacent and unselected memory cell disposed adjacent to the selected memory cell, the adjacent and unselected memory cell being completed in data write later than the selected memory cell, and a second read pass voltage higher than the first read pass voltage is applied to the adjacent and unselected memory cell.

Claims37

Dependent claims

A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:

a read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a selected voltage while unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
a first read pass voltage and a second read pass voltage higher than the first read pass voltage are generated by a voltage generation circuit, and wherein
the first read pass voltage generated by the voltage generation circuit is applied to unselected memory cells except adjacent and unselected memory cells disposed adjacent to the selected memory cell, and the second read pass voltage generated by the voltage generation circuit is applied to at least one of the adjacent and unselected memory cells in the read procedure.

A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:

a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;
and
a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell;
a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell;
and a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells;
the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell;
and a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the fourth read pass voltage being selected in level in accordance with the cell's threshold shift amount.

6 more elements

A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:

a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;
and
a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell;
a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and
in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell;
a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell's threshold shift amount, the maximum vale of which is higher than the first read pass voltage.

4 more elements

A non-volatile semiconductor memory device comprising:

a plurality of NAND strings each comprising a plurality of memory cells connected in series and formed in a surface of a semiconductor portion;
word lines respectively connected to each of the memory cells in each NAND string;
a first selection transistor respectively connected to a first end of each of the NAND strings;
a second selection transistor respectively connected to a second end of each of the NAND strings;
a bit line respectively connected to each of the first selection transistors;
a source line connected to each of the second selection transistors;
a first selection line connected to each first selection transistor;
a second selection line connected to each second selection transistor;
a plurality of page buffer circuits configured to read data of the bit lines in a read procedure;
and
a high voltage generation circuit configured to generate a first read voltage and a second read voltage supplied to the word lines, wherein
the second selection transistor is connected to a select gate having a first gate length in a direction perpendicular to a channel direction;
each of the word lines has a second gate length in the direction smaller than the first gate length;
each of the word lines comprises a first layer of conductive material having a dimension in a direction perpendicular to the surface of the semiconductor portion;
each of the gates of the second selection transistors comprises a second layer of conductive material having the dimension in the direction perpendicular to the surface of the semiconductor portion;
the second read voltage is set to be higher than the first read voltage;
the second read voltage is set to be higher than the first read voltage;
the first read voltage is applied to at least two of first unselected word lines except second unselected word lines disposed adjacent to a selected word line, and the second read voltage is applied to the second unselected word lines in the read procedure;
and
the first and second read voltages are sufficient to turn on unselected memory cells in the NAND string without regard to data of the unselected memory cells.

17 more elements

Dependencies are inferred from the claim text.

Non-volatile semiconductor memory device including application of different voltages to memory cells based on their proximity to a selected memory cell

Life of this patent

Non-volatile semiconductor memory device including application of different voltages to memory cells based on their proximity to a selected memory cell

Life of this patent

Abstract

Claims37