# US RE50,010 E1 · Clock gating circuit > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US RE50,010 E1 - Document ID: USRE50010E1 - Status: Granted - Kind: E1 - Application number: 17/672,371 - Filed: 2022-02-15 - Granted: 2024-06-11 - Earliest claimed: 2015-04-27 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Ah-Reum Kim; Hyun Lee; Min-su Kim - Web page: https://patentgrep.com/patent/USRE50010E1 ## CPC - H03K 19/01855: {synchronous, i.e. using clock signals} - H03K 3/012: Modifications of generator to improve response time or to decrease power consumption - H03K 3/037: Bistable circuits - H03K 3/356104: {using complementary field-effect transistors (H03K3/35625 takes precedence)} - H03K 3/356191: {with synchronous operation} - H03K 19/0013: {in field effect transistor circuits} - H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M) ## Abstract Provided are semiconductor circuits. A semiconductor circuit includes a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node. ## Claims ### Claim 1 A semiconductor circuit comprising: an input circuit configured to determine a voltage level of a first node; a first circuit configured to propagate a value of the first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node and determine a value of the third node based on the voltage level of the clock signal; a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal; and second node and the voltage level of the clock signal; and an output circuit configured to determine a voltage level of a fourth node based on a voltage level of the third node, wherein the first circuit includes a first transistor gated to the voltage level of the first node, a second transistor gated to the voltage level of the third node, and a third transistor gated to the voltage level of the of the clock signal, wherein the first transistor is connected with the second transistor in series, wherein one of a source or a drain of the first transistor is connected to an input from the first node, and wherein the second circuit includes an inverter inverting the second node, a fourth transistor gated to the voltage level of the clock signal, and wherein a source terminal of the first transistor is connected to an input from the first node output of the inverter, and a fifth transistor gated to the clock signal and connected with the fourth transistor. ### Claim 2 (depends on 1) The semiconductor circuit of claim 1, wherein when the first node is at a first voltage level and the clock signal is at the first voltage level, the first transistor is turned on and the second node is at a second voltage level. ### Claim 3 (depends on 1) The semiconductor circuit of claim 1, wherein when the first node is at a first voltage level and the clock signal is at a second voltage level, the first transistor is turned off and the voltage level of the second node is maintained. ### Claim 4 (depends on 1) The semiconductor circuit of claim 1, wherein when the clock signal is at a first voltage level, the third node receives a power supply voltage. ### Claim 5 (depends on 1) The semiconductor circuit of claim 1, wherein the output circuit includes an inverter configured to invert the voltage level of the third node. ### Claim 6 (depends on 1) The semiconductor circuit of claim 1, wherein the third transistor is connected in parallel with the first and second transistors. ### Claim 7 (depends on 1) The semiconductor circuit of claim 1, wherein the second transistor is connected in series with the first transistor, and the third transistor is connected in parallel with the first and second transistors. ### Claim 8 (depends on 1) The semiconductor circuit of claim 1, wherein the source terminal of the first transistor is connected to the first node through an inverter. ### Claim 9 A semiconductor circuit comprising: an input circuit configured to determine a voltage level of a first node; a first circuit configured to propagate a value of the first node to a second node based on a voltage level of a clock signal determine a voltage level of a second node based on the first node; a second circuit configured to propagate a value of the second node to a third node and determine a value of the third node based on the voltage level of the clock signal; a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal; and second node and a voltage level of a clock signal; an output circuit configured to determine a voltage level of a fourth node based on a voltage level of the third node, wherein the first circuit includes a first transistor gated to the voltage level of the first node, a second transistor gated to the voltage level of the third node, and a third transistor gated to the voltage level of the of the clock signal, wherein the first transistor is connected in series with the second transistor, wherein the second circuit includes an inverter inverting the second node and a fourth transistor gated to the voltage level of the clock signal, and wherein the second transistor is connected in series with the first transistor, and the third transistor is connected in parallel with the first and second transistors output of the inverter, wherein the third transistor is connected in parallel with the first and second transistors. ### Claim 10 A semiconductor circuit comprising: a first circuit including a first transistor configured to propagate an inverted voltage level of a first node to a second node when a clock signal is at a first voltage level; a second circuit including a second transistor configured to propagate an inverted voltage level of the second node to a third node when the clock signal is at a second voltage level; and a third circuit including a third transistor gated to a voltage level of the second node and configured to provide a power supply voltage to the third node, wherein a source terminal of the first transistor is connected to an input from the first node. ### Claim 11 (depends on 10) The semiconductor circuit of claim 10, wherein the first circuit includes a fourth transistor and a fifth transistor. ### Claim 12 (depends on 11) The semiconductor circuit of claim 11, wherein the fourth transistor is connected in parallel with the first transistor. ### Claim 13 (depends on 10) The semiconductor circuit of claim 10, wherein when the first node is at the first voltage level and the clock signal is at the first voltage level, the first transistor is turned on and the second node is at the second voltage level. ### Claim 14 (depends on 10) The semiconductor circuit of claim 10, wherein when the first node is at the first voltage level and the clock signal is at the second voltage level, the first transistor is turned off and a voltage level of the second node is maintained. ### Claim 15 (depends on 10) The semiconductor circuit of claim 10, wherein when the clock signal is at the first voltage level, the third node receives the power supply voltage. ### Claim 16 (depends on 10) The semiconductor circuit of claim 10, wherein the third transistor provides the power supply voltage to the third mode when the clock signal is changed from the first voltage level to the second voltage level. ### Claim 17 (depends on 10) The semiconductor circuit of claim 10, wherein the source terminal of the first transistor is connected to the first mode through an inverter. ### Claim 18 (depends on 1) The semiconductor circuit of claim 1, wherein the second circuit comprises a sixth transistor gated to the voltage level of the second node to provide a power supply voltage to the third node, and a seventh transistor connected in parallel with the sixth transistor and gated to the voltage level of the clock signal to provide the power supply voltage to the third node. ### Claim 19 (depends on 1) The semiconductor circuit of claim 1, wherein the third transistor is connected in parallel with the first and second transistors. ### Claim 20 (depends on 19) The semiconductor circuit of claim 19, wherein a drain of the fourth transistor is connected with a drain of the first transistor and the drain of the fourth transistor is connected with a source of the second transistor, wherein a source of the first transistor is connected to an input from the first node and a drain of the second transistor is connected to the second node. ### Claim 21 (depends on 1) The semiconductor circuit of claim 1, wherein a drain of the second transistor and the drain of a third transistor are connected to the second node. ### Claim 22 (depends on 1) The semiconductor circuit of claim 1, wherein the semiconductor circuit further comprising, a NAND gate conducting a NAND logical operation with the clock signal and the voltage level of the second node, wherein the NAND gate is connected between the second circuit and the output circuit. ### Claim 23 (depends on 1) The semiconductor circuit of claim 1, wherein a source of the fourth transistor is connected to a ground and a drain of the fourth transistor is connected to a source of the fifth transistor. ### Claim 24 (depends on 9) The semiconductor circuit of claim 9, wherein the second circuit includes a fifth transistor gated to the clock signal, wherein the fifth transistor is connected in series with the fourth transistor, and a source of the fourth transistor is connected with ground. ### Claim 25 (depends on 24) The semiconductor circuit of claim 24, wherein a drain of the fifth transistor is connected with the second node. ### Claim 26 (depends on 24) The semiconductor circuit of claim 24, wherein a drain of the fifth transistor is connected with the drain of the first transistor and a source of the second transistor. ### Claim 27 (depends on 9) The semiconductor circuit of claim 9, wherein a drain of the fourth transistor is connected with a drain of the first transistor and a source of the second transistor, and a source of the fourth transistor is connected with a drain of a sixth transistor. ### Claim 28 (depends on 9) The semiconductor circuit of claim 9, wherein the input circuit comprises a NOR gate. ### Claim 29 (depends on 9) The semiconductor circuit of claim 9, wherein the second circuit comprises a sixth transistor gated to the clock signal and connected with the inverter and the third node. ### Claim 30 (depends on 9) The semiconductor circuit of claim 9, wherein the second circuit comprises a sixth transistor gated to the clock signal and connected with the fourth transistor.