Dynamic measurement of frequency synthesizer noise spurs or phase noise

A circuit combination, comprising:

• a phase lock loop (PLL) frequency synthesizer including a first error detector including a first phase frequency detector (PFD) having an input for receiving a reference frequency signal coupled to a first charge pump (CP) that is coupled to a voltage controlled oscillator (VCO) having an output fed back to said first error detector after frequency division by a feedback divider to provide a divided frequency signal to another input of said first PFD, said first PFD outputting an error signal;
• phase noise (PN) measurement circuitry including:
• a replica CP coupled to an output of a second PFD or coupled to an output of said first PFD, wherein said replica CP is for outputting a scaled phase error current;
• a current-to-voltage converter and amplifier for current-to-voltage converting and amplifying said scaled phase error current to provide an amplified phase error voltage;
• an analog-to-digital converter (ADC) for digitizing said amplified phase error voltage to provide a digital phase error signal, and
• a processor for frequency analyzing said digital phase error signal for generating a PN measurement at one or more frequencies, and for comparing said PN measurement to a stored threshold noise measure to determine whether said frequency synthesizer is operating within a specified PN limit.

A circuit combination, comprising:

• a phase lock loop (PLL) frequency synthesizer including a first error detector including a first phase frequency detector (PFD) having an input for receiving a reference frequency signal coupled to a first charge pump (CP) that is coupled to a voltage controlled oscillator (VCO) having an output fed back to said first error detector after frequency division by a feedback divider to provide a divided frequency signal to another input of said first PFD, said first PFD outputting an error signal;
• phase noise (PN) measurement circuitry including:
• a replica phase noise (PN) measurement error detector including a second PFD coupled to a replica CP, wherein said replica CP is for outputting a scaled phase error current;
• a current-to-voltage converter and amplifier for current-to-voltage converting and amplifying said scaled phase error current to provide an amplified phase error voltage;
• an analog-to-digital converter (ADC) for digitizing said amplified phase error voltage to provide a digital phase error signal, and
• a processor for frequency analyzing said digital phase error signal for generating a PN measurement at one or more frequencies, wherein said processor is for comparing said PN measurement to a threshold noise measure to determine whether said frequency synthesizer is operating within a specified PN limit.

A circuit, comprising:

• a first phase frequency detector (PFD) having a first input, a second input, a first output, and a second output, the first input of the first PFD adapted to be coupled to a reference frequency signal generator;
• a first charge pump (CP) having an input and an output, the input of the first CP is coupled to the first output of the first PFD;
• a voltage controlled oscillator (VCO) having an input and an output, the input of the VCO coupled to the output of the first CP;
• a frequency divider having an input and an output, the input of the frequency divider coupled to the output of the VCO and the output of the frequency divider coupled to the input of the second input of the first PFD;
• and
• a second CP having an input and an output, the input of the second CP coupled to the second output of the first PFD;
• and
• an analog-to-digital converter (ADC) having an input and an output, the input coupled to the output of the second CP.