Generation of fast frequency ramps

A method comprising:

• generating an RF oscillator signal using an RF oscillator that is coupled in a phase-locked loop, the phase-locked loop configured to generate a feedback signal for the RF oscillator based on a digital input signal, which is a sequence of digital words;
• converting the digital input signal to an analog output signal, wherein the converting comprises reducing word-lengths of the digital words in the sequence of digital words, sigma-delta modulating the sequence of digital words having reduced word-lengths, and converting the modulated sequence of digital words of reduced word-lengths to obtain the analog output signal;
• and
• combining the analog output signal and the feedback signal to generate a control signal for the RF oscillator.

A circuit comprising:

• an RF oscillator coupled in a phase-locked loop, the phase-locked loop configured to receive a digital input signal, which is a sequence of digital words, and to generate an RF oscillator signal based on a control signal derived from the digital input signal, and generate a feedback signal for the RF oscillator based on the RF oscillator signal and the digital input signal;
• and
• a digital-to-analog conversion unit configured to receive the digital input signal and to generate an analog output signal, the digital-to-analog conversion unit comprising a pre-processing stage configured to pre-process the sequence of digital words and a digital-to-analog-converter configured to convert the pre-processed sequence of digital words into the analog output signal, and circuitry configured to combine the analog output signal and the feedback signal to generate a control signal for the RF oscillator,
• a compensation circuit comprising a pre-processing stage configured to receive and pre-process the sequence of digital words to generate an output signal, and circuitry configured to combine the output signal and the feedback signal to generate the control signal for the RF oscillator,
• wherein the pre-processing stage includes a word-length adaption unit processing circuit configured to generate the pre-processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and further includes a sigma-delta modulator coupled to the word-length adaption unit processing circuit downstream thereof, the sigma-delta modulator being configured to modulate the pre-processed sequence of sequence of digital words having reduced word-lengths and output the pre-processed sequence of digital words, as modulated, to the digital-to-analog-converter.

A circuit, comprising:

• a phase locked loop (PLL) configured to generate frequency modulated RF signals, the PLL comprising:
• a first loop path between a phase comparator and an RF output of the PLL, the first loop path comprising an RF oscillator;
• and
• a multi-modulus divider arranged in a feedback loop of the PLL;
• a first input to receive a digital input signal comprising a sequence of digital words related to frequency ramps of the frequency modulated RF signals;
• a first control path coupled to the first input and the multi-modulus divider, the first control path comprising a first sigma-delta modulator configured to generate a control signal for the multi-modulus divider to alter a division ratio of the multi-modulus divider based on the sequence of digital words;
• and
• a second control path coupled to the first input and the first loop path, the second control path comprising a pre-processing stage, the pre-processing stage comprising a pre-distortion processing circuit and a second sigma-delta modulator, wherein the pre-distortion processing circuit is configured to compensate for a non-linear characteristic of the RF oscillator.

A circuit, comprising:

• a phase locked loop (PLL) configured to generate frequency modulated RF signals, the PLL comprising:
• a first loop path between a phase comparator and an RF output of the PLL, the first loop path comprising an RF oscillator;
• and
• a multi-modulus divider arranged in a feedback loop of the PLL;
• a first input to receive a digital input signal comprising a sequence of digital words related to frequency ramps of the frequency modulated RF signals;
• a first control path coupled to the first input and the multi-modulus divider, the first control path comprising a first sigma-delta modulator configured to generate a control signal for the multi-modulus divider to alter a division ratio of the multi-modulus divider based on the sequence of digital words;
• and
• a second control path coupled to the first input and the first loop path, the second control path comprising a pre-processing stage, the pre-processing stage comprising a word-length adaption processing circuit configured to generate a processed sequence of digital words by reducing the word-lengths of the digital words in the sequence of digital words and comprising a pre-distortion processing circuit configured to compensate for a non-linear characteristic of the RF oscillator.