High/low speed mode selection for output driver circuits of a memory interface

An input/output interface for a memory device comprising:

• a mode selection circuit configured to generate a mode selection signal;
• a termination circuit configured to provide the input/output interface with one of a VSSQ termination, a VDDQ termination and a termination off mode in response to the mode selection signal;
• and
• an output driver block configured to transmit a data output signal, the output driver block being connected to an input/output pad and comprising a plurality of output driver circuits, wherein one of the plurality of output driver circuits is configured to selectively operate or not operate according to the mode selection signal, the mode selection signal indicating a termination type of the termination circuit,
• wherein each of the plurality of output driver circuits has different topology suitable for different operation speed, the operation speed selected from a group including a low speed operation, and a high speed operation faster than the low speed operation.

An input/output interface circuit for a memory device comprising:

• a mode selection circuit configured to generate a mode selection signal;
• a termination circuit configured to provide the input/output interface with one of a VSSQ termination, a VDDQ termination and a termination off mode in response to the mode selection signal;
• and
• an output driver block connected to an input/output pad including,
• a first output driver circuit configured to transmit a output data signal, the first output driver circuit including a NMOS pull-up driver;, and
• a second output driver circuit configured to transmit the output data signal, the second output driver circuit including a PMOS pull-up driver,
• wherein one of the first output driver circuit and the second output driver circuit is selected to transmit the output data signal in response to the mode selection signal.