US RE48,625 E1 · Memory circuit having non-volatile memory cell and methods of using

Abstract

One aspect relates to a memory circuit that has a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell and to configure a volatile output based on the program state of the NVM cell. The NVM cell comprises a first anti-fuse device, a first select device connected in series with the first anti-fuse device at a first node, and a first pass device. The memory circuit also may have a programmable (independently of the NVM cell) volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell. The NVM cell may have two NV elements that are separately programmable and are separately selectable via separate access transistors to drive the VM input node.

Claims23

Dependent claims

An article of manufacture comprising a memory circuit comprising:

volatile output circuitry (VOC);
and
a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:
a first anti-fuse device non-volatile memory element;
a second anti-fuse device non-volatile memory element;
a first select device connected in series with the first anti-fuse device non-volatile memory element at a first node, wherein the first select device has a first terminal and a second terminal;
a second select device connected in series with the second anti-fuse device non-volatile memory element at a second node, wherein the second select device has a first terminal and a second terminal, wherein the first select device's first terminal is connected to the second select device's first terminal, and wherein the first select device's second terminal is connected to the second select device's second terminal;
a first pass device connected between the first node and a VOC input node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the VOC input node;
and
a second pass device connected between the second node and the VOC input node and usable to selectively pass a voltage at the second node to the VOC input node, wherein the volatile output circuitry is connected to receive the NVM output signal from the NVM cell at the VOC input node and generate a VOC output signal indicative of the program state of the NVM cell.

7 more elements

A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:

a first anti-fuse device non-volatile memory element;
a second anti-fuse device non-volatile memory element;
a first select device connected in series with the first anti-fuse device non-volatile memory element at a first node;
a second select device connected in series with the second anti-fuse device non-volatile memory element at a second node;
a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node;
and
a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by:
turning off the first select device;
applying a read voltage to the first anti-fuse device's non-volatile memory element's gate;
and
turning on the first pass device to pass a the voltage at the first node to the NVM output node, wherein:
when the first anti-fuse device is blown non-volatile memory element is programmed, the voltage at the first node passed to the NVM output node will be at a first level;
when the first anti-fuse device is not blown non-volatile memory element is not programmed, the voltage at the first node passed to the NVM output node will be at a second level different from the first level;
and
turning off the first select device comprises turning off the first and the second select devices;
applying a read voltage to the first anti-fuse device's non-volatile memory element gate comprises applying read voltages to the gates of the first and the second anti-fuse devices non-volatile memory elements;
and
turning on the first pass device comprises turning on the first and the second pass devices to pass a shorted voltage at the first and second nodes to the NVM output node, wherein:
if the first anti-fuse device is blown non-volatile memory element is programmed and the second anti-fuse device is not blown non-volatile memory element is not programmed, the shorted voltage passed to the NVM output node will be at a the first level;
and
if the first anti-fuse device is not blown non-volatile memory element is not programmed and the second anti-fuse device is blown non-volatile memory element is programmed, the shorted voltage passed to the NVM output node will be at a the second level different from the first level.

18 more elements

A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:

a first anti-fuse device non-volatile memory element;
a second anti-fuse device non-volatile memory element;
a first select device connected in series with the first anti-fuse device non-volatile memory element at a first node;
a second select device connected in series with the second anti-fuse device non-volatile memory element at a second node;
a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node;
and
a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by:
turning off the first select device;
applying a read voltage to the first anti-fuse device's non-volatile memory element's gate;
and
turning on the first pass device to pass a the voltage at the first node to the NVM output node, wherein:
when the first anti-fuse device is blown non-volatile memory element is programmed, the voltage at the first node passed to the NVM output node will be at a first level;
when the first anti-fuse device is not blown non-volatile memory element is not programmed, the voltage at the first node passed to the NVM output node will be at a second level different from the first level;
reading an other bit value from the NVM cell by:
turning off the second select device;
applying a read voltage to the second anti-fuse device's non-volatile memory element's gate;
and turning on the second pass device to pass a the voltage at the second node to the NVM output node, wherein:
if the second anti-fuse device is blown non-volatile memory element is programmed, then the voltage at the second node passed to the NVM output node will be at a third level;
and
if the second anti-fuse device is not blown non-volatile memory element is not programmed, then the voltage at the second node passed to the NVM output node will be at a fourth level different from the third level.

17 more elements

A method for operating a programmable Non-Volatile Memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising:

a first anti-fuse device non-volatile memory element;
a second anti-fuse device non-volatile memory element;
a first select device connected in series with the first anti-fuse device non-volatile memory element at a first node;
a second select device connected in series with the second anti-fuse device non-volatile memory element at a second node;
a first pass device connected between the first node and a NVM output node of the volatile output circuitry and usable to selectively pass a voltage at the first node to the NVM output node;
and
a second pass device connected between the second node and the NVM output node and usable to selectively pass a voltage at the second node to the NVM output node, the method comprising reading a bit value from the NVM cell by:
turning off the first select device;
applying a read voltage to the first anti-fuse device's non-volatile memory element gate;
and
turning on the first pass device to pass a the voltage at the first node to the NVM output node, wherein:
when the first anti-fuse device is blown non-volatile memory element is programmed, the voltage at the first node passed to the NVM output node will be at a first level;
when the first anti-fuse device is not blown non-volatile memory element is not programmed, the voltage at the first node passed to the NVM output node will be at a second level different from the first level;
and
prior to reading the bit value from the NVM cell, programming the bit value into the NVM cell by:
turning off the first pass device;
and turning on the first select device to apply a programmable voltage level across a gate oxide layer of the first anti-fuse device non-volatile memory element to create a permanent breakdown path through the gate oxide layer of the first anti-fuse device non-volatile memory element.

14 more elements

An article of manufacture comprising a memory circuit comprising:

a programmable non-volatile memory (NVM) cell configured to generate an NVM output signal indicative of a program state of the NVM cell, the NVM cell comprising a first anti-fuse device non-volatile memory element, a first select device connected in series with the first anti-fuse device non-volatile memory element at a first node, and a first pass device;
a programmable volatile memory (VM) cell configured to receive the NVM output signal at a VM input node and to generate a VM output signal indicative of the program state of the VM cell, wherein the first pass device is connected between the first node and the VM input node and usable to selectively pass a voltage at the first node to the VM input node, and
control logic configured to (i) program the NVM cell by turning off the first pass device and turning on the first select device to apply a program voltage level across a gate oxide layer of the first anti-fuse device non-volatile memory element to create a permanent breakdown path through the gate oxide layer and to (ii) cause the VM cell to be configured by the programmed NVM cell by turning off the first select device, applying a read voltage to a gate of the first anti-fuse device non-volatile memory element, and turning on the first pass device to change the voltage at the VM input node using sufficient current flow through the gate oxide layer of the first anti-fuse device non-volatile memory element by an amount sufficient to flip the VM output signal.

Dependencies are inferred from the claim text.

Memory circuit having non-volatile memory cell and methods of using

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Memory circuit having non-volatile memory cell and methods of using

Life of this patent

Abstract

Claims23