Semiconductor memory device and driving method thereof

A semiconductor memory device, comprising:

• a variable delay configured to delay a clock;
• an output driver configured to receive and output data in response to the delayed clock;
• and
• a calibration controller configured to measure AC parameters of data and data strobe signal received from a chipset in response to a calibration command received from the chipset, and control the delay time of the variable delay according to measured values of the output AC parameters.

A method for driving a semiconductor memory device, comprising:

• receiving a calibration command from a chipset;
• transferring a first data and a first data strobe signal to the chipset in response to the calibration command;
• receiving measured values of output AC parameters from the chipset, wherein the measured values of output AC parameters are measured at the chipset by using the data and the data strobe signal;
• setting a delay value with respect to a clock in response to the measured values of the output AC parameters;
• delaying the clock by the delay value to output a delayed clock;
• and transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock.

A method for driving a semiconductor memory device, comprising:

• receiving a calibration command from a chipset;
• receiving a first data and a first data strobe signal from the chipset;
• measuring AC parameters of the first data and the first data strobe signal in response to the calibration command;
• controlling the delay time of a clock according to measured values of the AC parameters;
• and
• transferring a second data and a second data strobe signal having calibrated output AC parameters to the chipset in response to the delayed clock.

A memory system including a dynamic access memory and control system, the control system comprising:

• a variable delay unit for delaying a clock signal by a predetermined delay time to output a delayed clock signal;
• an output driver for transferring data and a data strobe signal in response to the delayed clock signal;
• and
• a calibration controller for controlling the predetermined delay time of the variable delay according to at least one output AC parameter, wherein the calibration controller comprises:
• a real-time monitoring buffer for monitoring the data and the data strobe signal;
• and
• a timing measurer for receiving the data and the data strobe signal from the real-time monitoring buffer and calibrating the predetermined delay time by measuring the at least one output AC parameter and controlling said measured AC parameter.

A method for driving a memory system, the system including a dynamic access memory and at least one signal driver outputting data strobe signals and data signals, the method comprising:

• receiving a calibration command from a chipset;
• receiving a first data strobe signal and a first data signal from the chipset;
• measuring at least one output AC parameter from one of the data strobe signal and data signal;
• setting a delay value with respect to a DLL clock signal in response to the measured values of the at least one output AC parameter;
• delaying the DLL clock signal by the delay value to output a delayed clock signal to the chipset;
• and
• transferring a second data strobe signal and a second data signal having a calibrated at least one output AC parameter to the chipset in response to the delayed clock signal,
• wherein the measuring of the at least one output AC parameter comprises:
• generating a calibration test mode signal in response to a calibration command;
• feeding back the data and the data strobe signal in response to the calibration test mode signal;
• and
• measuring the at least one output AC parameter by using the fed-back data strobe signal and the fed-back data.