Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKatsuyuki Fujita
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Abstract
According to one embodiment, a semiconductor memory device includes first word lines connected to a memory cell array, second word lines connected to a redundancy area, a first row decoder configured to perform selecting from the first word lines based on a row address, a judgment circuit configured to determine whether or not a replacement operation with the redundancy area is needed based on a redundancy address included in the row address, and a second row decoder configured to perform selecting from the second word lines. The row address includes a first row address and a second row address input in order in a time-sharing method. The first row address includes all of the redundancy address.
Claims34
A semiconductor memory device comprising:
- a memory cell array comprising memory cells;
- and
- a redundancy area comprising redundancy cells which are used for failure cells in the memory cell array;
- wherein:
- the semiconductor memory device receives an address from outside,
- the address includes a first portion, a second portion, and a third portion which are input in order and divided from each other,
- the first portion includes a redundancy address for the redundancy area,
- the first portion is input with a command, and
- a first time interval between the first portion and the second portion is different from a second time interval between the second portion and the third portion.
A semiconductor memory device comprising:
- a memory cell array comprising memory cells;
- and
- a redundancy area comprising redundancy cells which are used for failure cells in the memory cell array,
- wherein:
- the semiconductor memory device receives an address from outside,
- the address includes a first portion, a second portion, and a third portion which are input in order and divided from each other,
- the first portion includes a redundancy address for the redundancy area,
- the first portion is input with a command, and
- a number of cycles between the first portion and the second portion is different from a number of cycles between the second portion and the third portion.
A semiconductor memory device comprising:
- a memory cell array comprising memory cells;
- and
- a redundancy area comprising redundancy cells which are used for failure cells in the memory cell array,
- wherein:
- the semiconductor memory device receives an address from outside,
- the address includes a first portion, a second portion, and a third portion which are input in order and divided from each other,
- the first portion includes a redundancy address related to a redundancy replacement operation,
- the first portion is input with a command, and
- a first time interval between the first portion and the second portion is different from a second time interval between the second portion and the third portion.
A semiconductor memory device comprising:
- a memory cell array comprising memory cells;
- and
- a redundancy area comprising redundancy cells which are used for failure cells in the memory cell array,
- wherein:
- the semiconductor memory device receives an address from outside,
- the address includes a first portion, a second portion, and a third portion which are input in order and divided from each other,
- the first portion includes a redundancy address related to a redundancy replacement operation,
- the first portion is input with a command, and
- a number of cycles between the first portion and the second portion is different from a number of cycles between the second portion and the third portion.
Dependencies are inferred from the claim text.