Three-dimensionally stacked nonvolatile semiconductor memory

A semiconductor memory comprising:

• a semiconductor substrate;
• a stacked body disposed above the substrate, the stacked body including:
• a first conductive layer disposed above the semiconductor substrate and configured as a first word line,
• a second conductive layer disposed above the first conductive layer and configured as a second word line,
• a third conductive layer disposed above the second conductive layer and configured as a third word line, and
• a semiconductor column formed in a hole which penetrates the first conductive layer, the second conductive layer, and the third conductive layer in the stacked body, and extends in a first direction perpendicular to the semiconductor substrate;
• a first storage portion which surrounds the semiconductor column, is disposed between the first conductive layer and the semiconductor column, and is configured as a first memory cell, a gate of the first memory cell being electrically connected to the first word line, wherein the first word line, the first storage portion, and a portion of the semiconductor column surrounded by the first storage portion are disposed along a second direction parallel to the semiconductor substrate;
• a second storage portion which surrounds the semiconductor column, is disposed between the second conductive layer and the semiconductor column, and is configured as a second memory cell, a gate of the second memory cell being electrically connected to the second word line, wherein the second word line, the second storage portion, and a portion of the semiconductor column surrounded by the second storage portion are disposed along the second direction;
• a third storage portion which surrounds the semiconductor column, is disposed between the third conductive layer and the semiconductor column, and is configured as a third memory cell, a gate of the third memory cell being electrically connected to the third word line, wherein the third word line, the third storage portion, and a portion of the semiconductor column surrounded by the third storage portion are disposed along the second direction, and wherein the first memory cell, the second memory cell, and the third memory cell are connected in series and configured as a memory string;
• and
• a control circuit configured to perform a read operation on a condition that a first read voltage for reading first level data is applied to the first word line when the first word line is selected, a second read voltage for reading the first level data is applied to the second word line when the second word line is selected, or a third read voltage for reading the first level data is applied to the third word line when the third line is selected,
• wherein the third read voltage is larger than the second read voltage, and second voltage is larger than the first read voltage, and
• wherein a third diameter of the semiconductor column surrounded by the third storage portion in the second direction is larger than a second diameter of the semiconductor column surrounded by the second storage portion in the second direction, and the second diameter of the semiconductor column is larger than a first diameter of the semiconductor column surrounded by the first storage portion in the second direction.