Method for controlling a non-volatile semiconductor memory device

A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:

• a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;
• and
• a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
• in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except two adjacent and unselected memory cells disposed adjacent to the selected memory cell;
• a second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell;
• and a third read pass voltage lower than the first read pass voltage is applied to the other cell, which is written later than the selected memory cell, and
• in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the two adjacent and unselected memory cells;
• the second read pass voltage higher than the first read pass voltage is applied to one cell of the two adjacent and unselected memory cells, the one cell having been written previously to the selected memory cell;
• and a fourth read pass voltage is applied to the other cell, which has been written later than the selected memory cell, the fourth read pass voltage being selected in level in accordance with the cell's threshold shift amount.

A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:

• a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;
• and
• a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
• in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell;
• a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and
• in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell;
• a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell's threshold shift amount, the maximum vale of which is higher than the first read pass voltage.

A method for controlling a non-volatile semiconductor memory device having a NAND string, in which multiple memory cells are connected in series, comprising:

• a write-verifying procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a write-verifying voltage and unselected memory cells are driven to be turned on without regard to cell data thereof;
• and
• a normal read procedure performed for a selected memory cell in the NAND string on the condition that the selected memory cell is applied with a read voltage and unselected memory cells are driven to be turned on without regard to cell data thereof, wherein
• in the write-verifying procedure, a first read pass voltage is applied to unselected memory cells except adjacent and unselected memory cells adjacent to the selected memory cell;
• a second read pass voltage lower than the first read pass voltage is applied to one of the adjacent and unselected memory cells, which is written later than the selected memory cell, and
• in the normal read procedure, the first read pass voltage is applied to the unselected memory cells except the adjacent and unselected memory cells disposed adjacent to the selected memory cell;
• a third read pass voltage is applied to one of the adjacent and unselected memory cells, which has been written later than the selected memory cell, the third read voltage being selected in level in accordance with the cell data, the maximum value of which is higher than the first read pass voltage.

A non-volatile semiconductor memory device comprising:

• a NAND string including first to n-th memory cells (n is a natural number and is equal to or more than 2), the first to n-th memory cells being connected in series,
• first to n-th word lines electrically connected to the first to n-th memory cells,
• a voltage generation circuit configured to generate a selected voltage, a first voltage, and a second voltage, wherein
• the selected voltage is applied to the k-th word line(k is a natural number and range of k is from 3 to n−2), the first voltage is applied to both (k−1)-th word line and (k+1)-th word line, and the second voltage is applied to both (k−2)-th word line and (k+2)-th word line when a read procedure is executed, the first voltage being higher than the second voltage.

A method for controlling a non-volatile semiconductor memory device including a NAND string, in which multiple memory cells are connected in series, comprising:

• a read procedure performed for a selected memory cell in the NAND string on the condition that a selected voltage is applied to a selected word line and unselected voltages are applied to unselected word lines, the selected word line being connected to the selected memory cell, the unselected word lines being connected to unselected memory cells, the unselected voltages including a first voltage and a second voltage, the second voltage being higher than the first voltage, both the first voltage and the second voltage being generated by a voltage generation circuit, and
• wherein the first voltage generated by the voltage generation circuit is applied to the unselected word lines except adjacent and unselected word lines disposed adjacent to the selected word line, and the second voltage generated by the voltage generation circuit is applied to at least one of the adjacent and unselected word lines,
• wherein the multiple memory cells include a first memory cell and a second memory cell, the first memory cell being disposed adjacent to the second memory cell, the first and second memory cell being capable of holding four-level data defined by data level E, A, B and C (where, E<A<B<C), and
• wherein a write procedure including a lower page write mode and an upper page write mode is executed, the lower page write mode including a first lower page write mode and a second lower page write mode, the first lower page write mode being executed to the first memory cell, the second lower page write mode being executed to the second memory cell after the first lower page write mode, the upper page write mode being executed to the first memory cell after the second lower page write mode.