Programming method for non-volatile memory device

A method of programming a non-volatile memory device comprising a first memory cell connected to a wordline and a first bitline and a second memory cell connected to the wordline and a second bitline, wherein the first memory cell and second memory cell are multi-level non-volatile memory cells capable of being programmed to 1st through Mth data values, the method comprising:

• performing a programming operation during which the first memory cell is programmed to an ith data value among the 1st through Mth data values using a first programming pulse applied to the wordline, and the second memory cell is programmed to a jth data value among the 1st through Mth data values using a second programming pulse different from the first programming pulse and applied to the wordline, the programming operation comprising:
• simultaneously applying a first bitline voltage having a first level and corresponding to the ith data value to the first bitline, and a second bitline voltage having a second level different from the first level and corresponding to the jth data value to the second bitline;
• and
• performing a verifying operation on the first memory cell and second memory cell, wherein execution timing for the verifying operation varies in relation to the 1st through Mth data values,
• wherein a time interval required to apply both the first programming pulse and the second programming pulse to the wordline is sufficiently small to preclude substantial capacitive coupling between either the first memory cell and the second memory and at least one other memory cell physically proximate to the at least one of the first memory cell and the second memory cell.

An iterative method of programming memory cells of a multi-level cell non-volatile memory to one of a plurality of data values, the iterative method comprising multiple programming loops, wherein each programming loop comprises:

• applying a first programming pulse to a wordline of the non-volatile memory device, and applying a first bitline voltage corresponding to a first data value among a plurality of data values to a first bitline;
• applying a second programming pulse having a level different from a level of the first programming pulse to the wordline after applying the first programming pulse to the wordline, and applying a second bitline voltage corresponding to a second data value among the plurality of data values to a second bitline, and applying a third bitline voltage corresponding to a third data value among the plurality of data values to a third bitline, wherein the second bitline voltage is applied to the second bitline and the third bitline voltage is applied to the third bitline simultaneously, wherein the second bitline voltage is different from the third bitline voltage if the second data value and third data value are different;
• and
• after applying the second programming pulse, applying at least one of a sequence of verifying voltages to the first bitline and the second bitline, wherein a level of the at least one of the sequence of verifying voltages varies in accordance with a data value being programmed to the memory cell.

A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:

• performing a first program loop;
• and
• performing a second program loop;
• wherein the first program loop comprising:
• during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;
• and
• during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values,
• wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
• a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
• each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
• the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;
• physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell;
• the first programming pulse and the second programming pulse are successively applied to the wordline.

A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:

• during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;
• during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values;
• and
• during a verification time after the applying the first programming pulse and the second programming pulse, applying successively, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
• wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
• a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
• each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
• the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;
• physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell;
• the first programming pulse and the second programming pulse are successively applied.

A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:

• during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline corresponding to a first data value among the plurality of data values;
• during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline corresponding to a third data value among the plurality of data values;
• and
• during a verification time after the applying the first programming pulse and the second programming pulse, applying successively, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
• wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
• a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
• each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
• the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously;
• physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one second memory cell and at least one other memory cell adjacent to the at least one first memory cell;
• the first programming pulse and the second programming pulse are successively applied.

A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:

• during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline, the at least one first bitline corresponding to a first data value among the plurality of data values;
• during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline, the at least one second bitline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline, the at least one third bitline corresponding to a third data value among the plurality of data values;
• and
• during a verification time, applying, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
• wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
• a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
• each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
• the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,
• physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell, and
• the first programming pulse and the second programming pulse are successively applied.

A method of programming memory cells of a multi-level cell non-volatile memory device to one of a plurality of data values, the method comprising:

• during a first program time, applying a first programming pulse to a wordline connected to selected memory cells among the memory cells of the multi-level cell non-volatile memory device and a first bitline voltage to at least one first bitline connected to at least one first memory cell among the selected memory cells associated with the wordline, the at least one first bitline corresponding to a first data value among the plurality of data values;
• during a second program time, applying a second programming pulse to the wordline, a second bitline voltage to at least one second bitline connected to at least one second memory cell among the selected memory cells associated with the wordline, the at least one second bitline corresponding to a second data value among the plurality of data values, and a third bitline voltage to at least one third bitline connected to at least one third memory cell among the selected memory cells associated with the wordline, the at least one third bitline corresponding to a third data value among the plurality of data values;
• and
• during a verification time after the applying the first programming pulse and the second programming pulse, applying, to the wordline, a first wordline verification pulse corresponding to the first data value, a second wordline verification pulse corresponding to the second data value and a third wordline verification pulse corresponding to the third data value,
• wherein a voltage level of the second programming pulse is different from a voltage level of the first programming pulse,
• a level of the second bitline voltage is different from a level of the third bitline voltage if the second data value and the third data value are different,
• each of a level of the first bitline voltage, the level of the second bitline voltage and the level of the third bitline voltage is lower than a level of a program inhibit voltage,
• the second bitline voltage is applied to the at least one second bitline and the third bitline voltage is applied to the at least one third bitline simultaneously,
• physically proximate memory cells connected to the wordline in the multi-level cell nonvolatile memory device include the at least one first memory cell and at least one other memory cell adjacent to the at least one first memory cell, and
• the first programming pulse and the second programming pulse are successively applied.