# US RE46,141 E1 · Semiconductor device and timing control method for the same

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- Number: US RE46,141 E1
- Document ID: USRE46141E1
- Status: Granted
- Kind: E1
- Application number: 14/207,015
- Filed: 2014-03-12
- Granted: 2016-09-06
- Earliest claimed: 2007-10-26
- Assignees: PS4 Luxco S.a.r.l.
- Applicants: PS4 Luxco S.a.r.l.
- Inventors: Hideyuki Yoko; Ryuuji Takishita
- Web page: https://patentgrep.com/patent/USRE46141E1

## CPC

- G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- H03K 3/012: Modifications of generator to improve response time or to decrease power consumption
- H03K 3/356113: {using additional transistors in the input circuit}
- G11C 2207/2227: Standby or low power modes
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)

## Abstract

A semiconductor device includes a power-supply control portion and a latch portion. The power-supply control portion supplies power to an internal circuit in response to an input signal synchronized with rising of clock. The latch portion latches the input signal in synchronization with falling of the clock and supplies the latched input signal to the internal circuit.

## Claims

### Claim 1

A device comprising:
a first main power supply line receiving a first power voltage;
a first auxiliary power supply line;
a second main power supply line receiving a second power voltage;
a second auxiliary power supply line;
a first transistor inserted between the first main power supply line and the first auxiliary power supply line, and connecting, when rendered conductive, the first main power supply line with the first auxiliary power supply line;
a second transistor inserted between the second main power supply line and the second auxiliary power supply line, and connecting, when rendered conductive, the second main power supply line with the second auxiliary power supply line;
an internal circuit coupled between the first auxiliary power supply line and the second auxiliary power supply line, and activated in response to appearance of a voltage between the first auxiliary power supply line and the second auxiliary power supply line to perform a circuit operation on an input signal supplied thereto; and
a control circuit coupled to the first and second transistors and the internal circuit and including first, second and third circuit portions, the first circuit portion being responsive to a command signal to generate the input signal and supplying the input signal to both of the second and third circuit portions, the second circuit portion receiving the input signal and rendering the first and second transistors conductive in response to the input signal, and the third circuit portion receiving the input signal from the first circuit portion and supplying the input signal to the internal circuit after the first and second transistors have been rendered conductive,
wherein the control circuit receives a clock, the first circuit portion of the control circuit generates the input signal in response to one of rising and falling edges of the clock, the second circuit portion of the control circuit renders the first and second transistors conductive in response to the one of rising and falling edges of the clock, and the third circuit portion of the control circuit supplies the input signal to the internal circuit in response to the other of the rising and falling edges of the clock following the one of the rising and falling edges of the clock.

### Claim 2 (depends on 1)

The device as claimed in claim 1, wherein the control circuit receives a clock, the first circuit portion of the control circuit includes a decoder circuit receiving a plurality of bits as the command signal and decoding the command signal to generate the input signal in response to one of rise and fall edge of the clock signal.

### Claim 3 (depends on 1)

The device as claimed in claim 1, wherein the third circuit portion of the control circuit includes a latch circuit and a delay circuit, the latch circuit includes an input terminal coupled to the first circuit portion of the control circuit, an output terminal coupled to the internal circuit, a clock terminal receiving a first timing signal generated in response to the other of the rising and falling edges of the clock following the one of the rising and falling edges of the clock and a reset terminal coupled to the delay circuit, and the delay circuit receives the first timing signal, delays the first timing signal to generate a second timing signal and supplies the second timing signal to the reset terminal of the control circuit.

### Claim 4

A device comprising:
first and second power supply lines;
a first transistor coupled between the first and the second power supply lines, and connecting, when rendered conductive, the second power supply line with the first power supply line;
an internal circuit coupled to at least one of the first and the second power supply lines, and receiving an input signal;
a control circuit including first, second and third circuit portions, the first circuit portion being responsive to a command signal to generate an input signal and supplying the input signal to both of the second and third circuit portions, the second circuit portion coupled to the first transistor, receiving the input signal and supplying the input signal to the first transistor, and the third circuit portion coupled to the internal circuit, receiving the input signal, the third circuit portion supplying the input signal to the internal circuit after the first transistor has received the input signal supplied from the second circuit portion of the control circuit,
wherein the control circuit receives a clock, the first circuit portion of the control circuit generates the input signal in response to one of rising and falling edges of the clock, the second circuit portion of the control circuit supplies the input signal to the first transistor in response to the one of rising and falling edges of the clock, and the third circuit portion of the control circuit supplies the input signal to the internal circuit in response to the other of the rising and falling edges of the clock following the one of the rising and falling edges of the clock.

### Claim 5 (depends on 4)

The device as claimed in claim 4, wherein the control circuit receives a clock, the first circuit portion of the control circuit includes a decoder circuit receiving a plurality of bits as the command signal and decoding the command signal to generate the input signal in response to one of rise and fall edge of the clock signal.

### Claim 6 (depends on 4)

The device as claimed in claim 4, wherein the third circuit portion of the control circuit includes a latch circuit and a delay circuit, the latch circuit includes an input terminal coupled to the first circuit portion of the control circuit, an output terminal coupled to the internal circuit, a clock terminal receiving a first timing signal generated in response to the other of the rising and falling edges of the clock following the one of the rising and falling edges of the clock and a reset terminal coupled to the delay circuit, and the delay circuit receives the first timing signal, delays the first timing signal to generate a second timing signal and supplies the second timing signal to the reset terminal of the control circuit.

### Claim 7

A device comprising:
a first main power supply line receiving a first power voltage;
a first auxiliary power supply line;
a second main power supply line receiving a second power voltage;
a first transistor inserted between the first main power supply line and the first auxiliary power supply line, and connecting, when rendered conductive, the first main power supply line with the first auxiliary power supply line;
a control circuit including first, second and third circuit portions, the first circuit portion being responsive to a command signal to generate an input signal and supplying the input signal to both the second and third circuit portions, the second circuit portion receiving the input signal and rendering the first transistor conductive in response to the input signal, and the third circuit portion receiving at a first input node thereof the input signal from the first circuit portion and at a second input node thereof a clock and transferring the input signal to an output node thereof in response to the clock after the first transistor has been rendered conductive; and
an internal circuit including a first power node coupled to the first auxiliary power supply line, a second power node coupled to the second power supply line and an input terminal coupled to the output node of the third circuit portion of the control circuit, the internal circuit being activated by the second circuit portion rendering the first transistor conductive in response to the input signal and thereafter performing a circuit operation on the input signal transferred through the input terminal from the third circuit portion,
wherein the control circuit receives the clock, the first circuit portion of the control circuit generates the input signal in response to one of rising and falling edges of the clock, the second circuit portion of the control circuit renders the first transistor conductive in response to the one of rising and falling edges of the clock, and the third circuit portion of the control circuit supplies the input signal to the internal circuit in response to the other of the rising and falling edges of the clock following the one of the rising and falling edges of the clock.

### Claim 8 (depends on 7)

The device as claimed in claim 7, wherein the control circuit receives the clock, the first circuit portion of the control circuit includes a decoder circuit receiving a plurality of bits of signal as the command signal and decoding the command signal to generate the input signal in response to one of rise and fall edge of the clock signal.

### Claim 9 (depends on 7)

The device as claimed in claim 7, wherein the third circuit portion of the control circuit includes a latch circuit and a delay circuit, the latch circuit includes an input terminal coupled to the first circuit portion of the control circuit, an output terminal coupled to the internal circuit, a clock terminal receiving a first timing signal generated in response to the other of the rising and falling edges of the clock following the one of the rising and falling edges of the clock and a reset terminal coupled to the delay circuit, and the delay circuit receives the first timing signal, delays the first timing signal to generate a second timing signal and supplies the second timing signal to the reset terminal of the control circuit.

### Claim 10 (depends on 8)

The device as claimed in claim 8, further comprising
a second main power supply line receiving a second power voltage;
a second auxiliary power supply line; and
a second transistor inserted between the second main power supply line and the second auxiliary power supply line, and connecting, when rendered conductive, the second main power supply line with the second auxiliary power supply line, and
wherein the second circuit portion of the control circuit further renders the second transistor conductive in response to the input signal and the internal circuit is further includes a second power node coupled to the second auxiliary power supply line.

### Claim 11

A method for operating a synchronous DRAM memory device having a low power standby state, the method comprising;
receiving a command in synchronization with a first edge of an external clock;
decoding the command to provide an internal command signal;
activating an internal circuit corresponding to the internal command signal by enabling a first source transistor to connect a main supply to the internal circuit so that the internal circuit exits the low power standby state and enters an active state; and
providing the internal command signal to the internal circuit in response to a second edge of the external clock that is opposite the first edge.

### Claim 12 (depends on 11)

The method as claimed in claim 11 wherein the first edge is a rising edge and the second edge is a falling edge.

### Claim 13 (depends on 11)

The method as claimed in claim 11 wherein the second edge is the next edge following the first edge.

### Claim 14 (depends on 11)

The method as claimed in claim 11 wherein the command is an active command and the internal circuit is a RAS control circuit.

### Claim 15 (depends on 11)

The method as claimed in claim 11 wherein the command is a read/write command and the internal circuit is a CAS control circuit.

### Claim 16 (depends on 11)

The method as claimed in claim 11 wherein the main supply is a main power supply.

### Claim 17 (depends on 11)

The method as claimed in claim 11 wherein the main supply is a main ground.

### Claim 18 (depends on 11)

The method as claimed in claim 11 wherein the main supply is a main power supply and the activating of the internal circuit further includes enabling a second source transistor to connect a main ground to the internal circuit.

### Claim 19 (depends on 18)

The method as claimed in claim 18 wherein a single source transistor driver circuit enables the first and second source transistors.

### Claim 20 (depends on 18)

The method as claimed in claim 18 wherein a first source transistor driver enables the first source transistor and a second source transistor driver enables the second source transistor.

### Claim 21 (depends on 18)

The method as claimed in claim 18 wherein the internal circuit includes: i) a third transistor directly connected to the main power supply; ii) a fourth transistor connected to the main power supply through the first source transistor; iii) a fifth transistor directly connected to the main ground; and iv) a sixth transistor connected to the main ground through the second source transistor.

### Claim 22 (depends on 21)

The method as claimed in claim 21 wherein the third transistor and the sixth transistor are part of a second logic element and the fourth transistor and the fifth transistor are part of a first logic element.

### Claim 23 (depends on 22)

The method as claimed in claim 22 wherein an output of the first logic element is connected to an input of the second logic element.

### Claim 24 (depends on 11)

The method as claimed in claim 11 wherein a latch provides the internal command signal to the internal circuit.

### Claim 25 (depends on 11)

The method as claimed in claim 11 wherein a through latch provides the internal command signal to the internal circuit.

### Claim 26 (depends on 11)

The method as claimed in claim 11 wherein the synchronous DRAM memory device is a DDR SDRAM.

### Claim 27 (depends on 11)

The method as claimed in claim 11 wherein the synchronous DRAM memory device is an LPDDR SDRAM.