US RE45,972 E1 · Nonvolatile semiconductor memory device

A nonvolatile semiconductor memory device comprising:

a memory unit;
and
a control unit,
the memory unit including a first memory string, a first wiring, a second memory string, and a second wiring,
the first memory string including a first memory cell group and a first select transistor,
the first memory cell group including a plurality of first memory transistors connected in series,
each of the plurality of first memory transistors including a channel formed in a first semiconductor layer, including a first control gate, and allowing data of the each of the plurality of first memory transistors to be electrically rewritten,
the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate,
the first wiring being connected to the first semiconductor layer on a side of the first select transistor opposite to the first memory cell group,
the second memory string including a second memory cell group and a second select transistor,
the second memory cell group including a plurality of second memory transistors connected in series,
each of the plurality of second memory transistors including a channel formed in a second semiconductor layer electrically isolated from the first semiconductor layer, including a control gate electrically connected to the first control gate, and allowing data of the each of the plurality of second memory transistors to be electrically rewritten,
the second select transistor being provided on one end side of the second memory cell group, including a channel formed in the second semiconductor layer, and including a select gate connected to the first select gate,
the second wiring being connected to the second semiconductor layer on a side of the second select transistor opposite to the second memory cell group,
in a selective erase operation for performing at least one of injection of a hole into a charge retention layer of a selected cell transistor in the selective erase operation of the first memory transistors and extraction of an electron from the charge retention layer of the selected cell transistor in the selective erase operation, the control unit being configured to:
apply a first voltage to the first wiring,
apply a second voltage lower than the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective erase operation,
apply a third voltage not higher than the first voltage and higher than the second voltage to a non-selected cell gate in the selective erase operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective erase operation,
apply the first voltage or a fourth voltage not higher than the first voltage and not lower than the third voltage to the first select gate, and
apply the second voltage or a fifth voltage higher than the second voltage and not higher than the third voltage to the second wiring or set the second wiring in a floating state.

17 more elements

A nonvolatile semiconductor memory device comprising:

a memory unit;
and
a control unit,
the memory unit including a first memory string, a first wiring, a first other wiring, and a first base wiring,
the first memory string including a first memory cell group, a first other memory cell group, a first select transistor, a first other select transistor, and a first connecting portion transistor,
the first memory cell group including a plurality of first memory transistors connected in series,
each of the plurality of first memory transistors including a channel formed in a first semiconductor layer provided in contact with a first base semiconductor layer, including a first control gate, and allowing data of the each of the plurality of first memory transistors to be electrically rewritten,
the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate,
the first other select transistor being provided on a side of the first memory cell group opposite to the first select transistor, including a channel formed in the first semiconductor layer, and including a first other select gate,
the first connecting portion transistor being provided between the first memory cell group and the first other select transistor, including a channel formed in the first semiconductor layer, and including a first connecting portion gate,
the first other memory cell group being provided between the first other select transistor and the first connecting portion transistor and including a plurality of first other memory transistors connected in series,
each of the plurality of first other memory transistors including a channel formed in the first semiconductor layer, including a first other control gate, and allowing data of the each of the plurality of first other memory transistors to be electrically rewritten,
the first wiring being connected to the first semiconductor layer on a side of the first select transistor opposite to the first memory cell group,
the first other wiring being connected to the first semiconductor layer on a side of the first other select transistor opposite to the first other memory cell group,
the first base wiring being connected to the first base semiconductor layer,
in a selective erase operation for performing at least one of injection of a hole into a charge retention layer of a selected cell transistor in the selective erase operation of the first memory transistors and extraction of an electron from the charge retention layer of the selected cell transistor in the selective erase operation, the control unit being configured to:
apply a first voltage to the first wiring and the first other wiring or set the first wiring and the first other wiring in a floating state,
apply a second voltage lower than the first voltage to a selected cell gate of the first control gate of the selected cell transistor in the selective erase operation,
apply a third voltage lower than the first voltage and higher than the second voltage to a non-selected cell gate in the selective erase operation of the first control gate of the first memory transistors other than the selected cell transistor in the selective erase operation,
apply the third voltage to the first other control gate,
apply a tenth voltage lower than the first voltage and higher than the second voltage to the first select gate and the first other select gate,
apply an eleventh voltage lower than the first voltage and higher than the second voltage to the first connecting portion gate, and
apply the first voltage to the first base wiring.

20 more elements

A nonvolatile semiconductor memory device comprising:

a memory unit;
and
a control unit,
the memory unit including a first memory string, a first wiring, a second memory string, a second wiring, a third memory string, a first other wiring, and a second other wiring,
the first memory string including a first memory cell group, a first select transistor, a first other memory cell group, a first other select transistor, and a first connecting portion transistor,
the first memory cell group including a plurality of first memory transistors connected in series,
each of the plurality of first memory transistors including a channel formed in a first semiconductor layer, including a first control gate, and allowing data to be electrically rewritten,
the first select transistor being provided on one end side of the first memory cell group, including a channel formed in the first semiconductor layer, and including a first select gate,
the first other select transistor being provided on a side of the first memory cell group opposite to the first select transistor, including a channel formed in the first semiconductor layer, and including a first other select gate,
the first connecting portion transistor being provided between the first memory cell group and the first other select transistor, including a channel formed in the first semiconductor layer, and including a first connecting portion gate,
the first other memory cell group being provided between the first other select transistor and the first connecting portion transistor, and including a plurality of first other memory transistors connected in series,
each of the plurality of first other memory transistors including a channel formed in the first semiconductor layer, including a first other control gate, and allowing data to be electrically rewritten,
the second memory string including a second memory cell group, a second select transistor, a second other memory cell group, a second other select transistor, and a second connecting portion transistor,
the second memory cell group including a plurality of second memory transistors connected in series,
each of the plurality of second memory transistors including a channel formed in a second semiconductor layer electrically isolated from the first semiconductor layer, including a second control gate, and allowing data to be electrically rewritten,
the second select transistor being provided on one end side of the second memory cell group, including a channel formed in the second semiconductor layer, and including a second select gate,
the second other select transistor being provided on a side of the second memory cell group opposite to the second select transistor, including a channel formed in the second semiconductor layer, and including a second other select gate,
the second connecting portion transistor being provided between the second memory cell group and the second other select transistor, including a channel formed in the second semiconductor layer, and including a connecting portion gate electrically connected to the first connecting portion gate,
the second other memory cell group being provided between the second other select transistor and the second connecting portion transistor, and including a plurality of second other memory transistors connected in series,
each of the plurality of second other memory transistors including a channel formed in the second semiconductor layer, including a control gate electrically connected to the first other control gate, and allowing data to be electrically rewritten,
the third memory string including a third memory cell group, a third select transistor, a third other memory cell group, a third other select transistor, and a third connecting portion transistor,
the third memory cell group including a plurality of third memory transistors connected in series,
each of the plurality of third memory transistors including a channel formed in a third semiconductor layer electrically isolated from the first semiconductor layer and the second semiconductor layer, including a control gate electrically connected to the first control gate, and allowing data to be electrically rewritten,
the third select transistor being provided on one end side of the third memory cell group, including a channel formed in the third semiconductor layer, and including a select gate connected to the first select gate,
the third other select transistor being provided on a side of the third memory cell group opposite to the third select transistor, including a channel formed in the third semiconductor layer, and including a select gate connected to the first other select gate,
the third connecting portion transistor being provided between the third memory cell group and the third other select transistor, including a channel formed in the third semiconductor layer, and including a second connecting portion gate,
the third other memory cell group being provided between the third other select transistor and the third connecting portion transistor and including a plurality of third other memory transistors connected in series,
each of the plurality of third other memory transistors including a channel formed in the third semiconductor layer, being electrically connected to the first other control gate, and allowing data to be electrically rewritten,
the first wiring being connected to the first semiconductor layer on a side of the first select transistor opposite to the first memory cell group, and being connected to the second semiconductor layer on a side of the second select transistor opposite to the second memory cell group,
the second wiring being connected to the third semiconductor layer on a side of the third select transistor opposite to the third memory cell group,
the first other wiring being connected to the first semiconductor layer on a side of the first other select transistor opposite to the first other memory cell group, and being connected to the third semiconductor layer on a side of the third other select transistor opposite to the third other memory cell group,
the second other wiring being connected to the second semiconductor layer on a side of the second other select transistor opposite to the second other memory cell group,
in a selective erase operation for performing at least one of injection of a hole into a charge retention layer of a selected cell transistor of the first memory transistors and extraction of an electron from the charge retention layer, the control unit being configured to:
apply a first voltage to the first wiring,
apply a second voltage lower than the first voltage to a selected cell gate of the selected cell transistor,
apply a third voltage not higher than the first voltage and higher than the second voltage to a non-selected cell gate of the first memory transistors other than the selected cell transistor,
apply a fourth voltage not higher than the first voltage and not lower than the third voltage to the first select gate,
apply the second voltage or a fifth voltage higher than the second voltage and not higher than the third voltage to the second wiring,
apply a sixth voltage lower than the third voltage to the second control gate of the second memory transistors,
apply a seventh voltage lower than the third voltage to the second select gate,
apply the fifth voltage or the second voltage to the first other wiring,
apply the third voltage to the first other control gate,
apply an eighth voltage lower than the third voltage to the first other select gate,
apply a ninth voltage lower than the first voltage and higher than the second voltage to the first connecting portion gate,
apply the second voltage to the second other wiring,
apply the sixth voltage to the second control gate,
apply the eighth voltage to the second select gate, and
apply the eighth voltage to the second other select gate.

45 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell provided at a first semiconductor layer extending in a first direction, the second memory string including a second memory cell provided at a second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a second bit line electrically connected with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer;
a second source line electrically connected with the second semiconductor layer;
a second wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second bit line in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being higher than the second voltage,
the first memory string further including a first transistor provided at the first semiconductor layer, the first transistor being connected with one end of the first memory cell,
the second memory string further including a second transistor provided at the second semiconductor layer, the second transistor being connected with one end of the second memory cell,
the second wiring member being connected with the first transistor and with the second transistor, and
the control circuit applies a sixth voltage to the second wiring member in the erase operation, and the sixth voltage is lower than the first voltage,
wherein
the control circuit applies a fourth voltage to the first source line in the erase operation, the fourth voltage is higher than the second voltage, and
the fourth voltage is higher than the third voltage in the erase operation.

18 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell provided at a first semiconductor layer extending in a first direction, the second memory string including a second memory cell provided at a second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a second bit line electrically connected with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer;
a second source line electrically connected with the second semiconductor layer;
a third wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second bit line in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being higher than the second voltage,
the first memory string further including a third transistor provided at the first semiconductor layer, the third transistor being connected with one end of the first memory cell,
the second memory string further including a fourth transistor provided at the second semiconductor layer, the fourth transistor being connected with one end of the second memory cell, and
the third wiring member being connected with the third transistor and with the fourth transistor,
wherein
the control circuit applies a seventh voltage to the third wiring member in the erase operation, and the seventh voltage is lower than the first voltage.

16 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell provided at a first semiconductor layer extending in a first direction, the second memory string including a second memory cell provided at a second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a second bit line electrically connected with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer;
a second source line electrically connected with the second semiconductor layer;
a fourth wiring member;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second bit line in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being higher than the second voltage,
the memory cell array further including a third memory string,
the third memory string further including a third memory cell provided at a third semiconductor layer extending in the first direction,
the first bit line being further electrically connected with the third semiconductor layer, and
the fourth wiring member being connected with the third memory cell, and
the control circuit applying an eighth voltage to the fourth wiring member in the erase operation, and the eighth voltage being lower than the first voltage.

16 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string, the first memory string including a first memory cell and a second memory cell, the first memory cell being provided at a first position of a first semiconductor layer, the second memory cell being provided at a second position of the first semiconductor layer, the first semiconductor layer extending in a first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell;
a second wiring member extending in the second direction, the second wiring member being connected with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a first source line electrically connected with the first semiconductor layer;
a fourth wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second wiring member in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being higher than the second voltage,
the first memory string further including a second transistor provided at the first semiconductor layer, the second transistor being connected with one end of the first memory cell, and
the fourth wiring member being connected with the second transistor,
wherein
the control circuit applies a sixth voltage to the fourth wiring member in the erase operation, and the sixth voltage is lower than the first voltage.

14 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell provided at a portion of a first semiconductor layer, the portion of the first semiconductor layer extending in a first direction, the second memory string including a second memory cell provided at a portion of a second semiconductor layer, the second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the second memory cell;
a first bit line electrically connected with the first semiconductor layer and with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer;
a second source line electrically connected with the second semiconductor layer;
a second wiring member extending in the second direction;
a third wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring member in the erase operation,
applying a third voltage to the second source line in the erase operation, and
applying a fourth voltage to the first source line in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being lower than the first voltage, and
the fourth voltage being lower than the first voltage,
the first memory string further including a first transistor provided at the first semiconductor layer, the first transistor being connected with one end of the first memory cell,
the second memory string further including a second transistor provided at the second semiconductor layer, the second transistor being connected with one end of the second memory cell,
the second wiring member being connected with the second transistor, and
the third wiring member being connected with the first transistor,
wherein
the control circuit applies a fifth voltage to the third wiring member in the erase operation, and the fifth voltage is lower than the first voltage.

19 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell provided at a portion of a first semiconductor layer, the portion of the first semiconductor layer extending in a first direction, the second memory string including a second memory cell provided at a portion of a second semiconductor layer, the portion of the second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the second memory cell,
a first bit line electrically connected with the first semiconductor layer and with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer;
a second source line electrically connected with the second semiconductor layer;
a fourth wiring member extending in the second direction;
a fifth wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring member in the erase operation,
applying a third voltage to the second source line in the erase operation, and
applying a fourth voltage to the first source line in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being lower than the first voltage, and
the fourth voltage being lower than the first voltage,
the first memory string further including a third transistor provided at the first semiconductor layer, the third transistor being connected with one end of the first memory cell,
the second memory string further including a fourth transistor provided at the second semiconductor layer, the fourth transistor being connected with one end of the second memory cell,
the fourth wiring member being connected with the third transistor, and
the fifth wiring member being connected with the fourth transistor.

17 more elements

A nonvolatile semiconductor memory device comprising;

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell provided at a portion of a first semiconductor layer, the portion of the first semiconductor layer extending in a first direction, the second memory string including a second memory cell provided at a portion of a second semiconductor layer, the portion of the second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the second memory cell;
a first bit line electrically connected with the first semiconductor layer and with the second semiconductor layer;
a second bit line;
a first source line electrically connected with the first semiconductor layer;
a second source line electrically connected with the second semiconductor layer;
a fifth wiring member;
and
a control circuit
applying a first voltage to the first bit line in an erase operation,
applying a second voltage to the first wiring in the erase operation,
applying a third voltage to the second source line in the erase operation, and
applying a fourth voltage to the first source line in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being lower than the first voltage,
the fourth voltage being lower than the first voltage,
the memory cell array further including a third memory string,
the third memory string including a third memory cell provided at a third semiconductor layer,
the second bit line being electrically connected with the third semiconductor layer,
the first wiring member being further connected with the third memory cell,
the control circuit applying a ninth voltage to the second bit line in the erase operation, and the ninth voltage being lower than the first voltage,
the third memory string further including a fifth transistor provided at the third semiconductor layer, the fifth transistor being connected with one end of the third memory cell, and
the fifth wiring member being connected with the fifth transistor.

20 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell and a second memory cell, the first memory cell being provided at a first position of a portion of a first semiconductor layer, the second memory cell being provided at a second position of the portion of the first semiconductor layer, the portion of the first semiconductor layer extending in a first direction, the second memory string including a third memory cell provided at a portion of a second semiconductor layer, the portion of the second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the third memory cell;
a second wiring member extending in the second direction, the second wiring member being connected with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a second bit line electrically connected with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer and with the second semiconductor layer;
a fourth wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in the erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second wiring member in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being higher than the second voltage,
the first memory string further including a third transistor provided at the first semiconductor layer, the third transistor being connected with one end of the first memory cell, and
the fourth wiring member being connected with the third transistor.

13 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell and a second memory cell, the first memory cell being provided at a first position of a portion of a first semiconductor layer, the second memory cell being provided at a second position of the portion of the first semiconductor layer, the portion of the first semiconductor layer extending in a first direction, the second memory string including a third memory cell provided at a portion of a second semiconductor layer, the second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the third memory cell;
a second wiring member extending in the second direction, the second wiring member being connected with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a second bit line electrically connected with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer and with the second semiconductor layer;
and
a control circuit
applying a first voltage to the first bit line in the erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second wiring member in the erase operation,
the second voltage being lower than the first voltage, and
the third voltage being higher than the second voltage,
wherein
the second memory string further includes a fourth memory cell provided at the second semiconductor layer, the second wiring member being connected with the fourth memory cell,
the control circuit applies a fourth voltage to the first source line in the erase operation, and the fourth voltage is higher than the second voltage, and
the first voltage is equal to the fourth voltage.

14 more elements

A nonvolatile semiconductor memory device comprising:

a memory array including a first memory string and a second memory string, the first memory string including a first memory cell and a second memory cell, the first memory cell being provided at a first position of a portion of a first semiconductor layer, the second memory cell being provided at a second position of the portion of the first semiconductor layer, the portion of the first semiconductor layer extending in a first direction, the second memory string including a third memory cell provided at a portion of a second semiconductor layer, the portion of the second semiconductor layer extending in the first direction;
a first wiring member extending in a second direction crossing the first direction, the first wiring member being connected with the first memory cell and with the third memory cell;
a second wiring member extending in the second direction, the second wiring member being connected with the second memory cell;
a first bit line electrically connected with the first semiconductor layer;
a second bit line electrically connected with the second semiconductor layer;
a first source line electrically connected with the first semiconductor layer and with the second semiconductor layer;
a second source line;
a fifth wiring member extending in the second direction;
a sixth wiring member extending in the second direction;
and
a control circuit
applying a first voltage to the first bit line in the erase operation,
applying a second voltage to the first wiring member in the erase operation, and
applying a third voltage to the second wiring member in the erase operation,
the second voltage being lower than the first voltage,
the third voltage being higher than the second voltage,
the memory array further including a third memory string, the third memory string including a fifth memory cell and a sixth memory cell, the fifth memory cell being provided at a fifth position of a third semiconductor layer, the sixth memory cell being provided at a sixth position of the third semiconductor layer, the third semiconductor layer extending in the first direction,
the first bit line being electrically connected with the third semiconductor layer,
the second source line being electrically connected with the third semiconductor layer,
the third memory string including a fifth transistor provided at the third semiconductor layer, the fifth transistor being connected with one end of the fifth memory cell,
the fifth wiring member being connected with the fifth transistor,
the third memory string further including a sixth transistor provided at the third semiconductor layer, the sixth transistor being connected with other end of the fifth memory cell, and
the sixth wiring member being connected with the sixth transistor.

20 more elements

Nonvolatile semiconductor memory device

Life of this patent

Nonvolatile semiconductor memory device

Life of this patent

Abstract

Claims61