Dual function system and method for shuffling packed data elements

A method comprising the computer-implemented steps of:

• decoding a single instruction;
• in response to the step of decoding the single instruction,
• accessing a first packed data operand having at least two data elements;
• accessing a second packed data operand having at least two data elements;
• selecting a first set of data elements from the first packed data operand;
• copying each of the data elements in the first set to specified data fields located in the lower half of a destination operand;
• selecting a second set of data elements from the second packed data operand;
• and
• copying each of the data elements in the second set to specified data fields located in the upper half of the destination operand.

A method comprising the computer implemented steps of:

• accessing data representative of a first three-dimensional image;
• altering the data using three-dimensional geometry to generate a second
• three-dimensional image, the step of altering at least including,
• accessing a first packed data operand having at least two data elements;
• accessing a second packed data operand having at least two data elements;
• selecting a first set of data elements from the first packed data operand;
• copying each of the data elements in the first set to specified data fields located in the lower half of a destination operand;
• selecting a second set of data elements from the second packed data operand;
• copying each of the data elements in the second set to specified data fields located in the upper half of the destination operand;
• and
• displaying the second three-dimensional image.

A method comprising the computer implemented steps of:

• accessing data representative of a first three-dimensional image;
• altering the data using three-dimensional geometry to generate a second three-dimensional image, the step of altering at least including,
• accessing a first packed data operand having at least two data elements;
• accessing a second packed data operand having at least two data elements;
• selecting a first set of data elements from the first packed data operand;
• copying each of the data elements in the first set to specified data fields located in the lower half of a destination operand;
• selecting a second set of data elements from the second packed data operand;
• copying each of the data elements in the second set to specified data fields located in the upper half of the destination operand;
• and
• displaying the second three-dimensional image.

A processor-implemented method for reducing the number of control hits required to shuffle packed data elements from first and second source operands, comprising the steps of:

• decoding a single instruction specifying first and second source operands and a field of control bits;
• and
• responsive to the field of control bits, generating a resultant packed data operand comprised of packed data elements from the first and second source operands,
• wherein the control bits are limited to specifying for the upper and lower halves of the resultant packed data operand, data elements from the first and second source operands, respectively.

A processor for performing a shuffle operation in response to a shuffle instruction comprising:

• a decoder which decodes a single instruction specifying first and second source operands and a field of control bits;
• and
• an execution unit which, responsive to the field of control bits, generates a resultant packed data operand comprised of packed data elements from the first and second source operands,
• wherein the control bits are limited to specifying for the upper and lower halves of the resultant packed data operand, data elements from the first and second source operands, respectively.

An apparatus comprising:

• a decode unit to decode a shuffle instruction into control signals, said shuffle instruction to include a first operand, a second operand, and a third operand wherein said third operand comprises of an 8-bit immediate value;
• said first operand to identify a first register to hold at least two packed data elements;
• said second operand to identify a memory location to hold at least two packed data elements;
• said third operand is to provide selection bits to indicate which of said packed data elements in said first operand and said second operand to select and copy to a resultant register;
• and
• an execution unit coupled to said decode unit, said execution unit responsive to said control signals and said selection bits to select a first set of data elements from said first register and to copy said first set of data elements to one or more lower destination fields of said resultant register, said execution unit further responsive to said control signals and said selection bits to select a second set of data elements from said memory location and to copy said second set of data elements to one or more upper destination fields of said resultant register.

An apparatus comprising:

• an instruction decoder to receive and decode a shuffle instruction, said shuffle instruction to include an immediate operand comprising two or more sets of control bits;
• a first source register to hold a first packed data, said first packed data comprising of a first data element and a second data element;
• a second source register to hold a second packed data, said second packed data comprising of a third data element and a fourth data element;
• a destination register to hold a third packed data;
• an execution unit coupled to said first source resister to receive said first packed data, and to said second source register to receive said second packed data;
• and
• wherein said execution unit is further coupled to said instruction decoder to receive said two or more sets of control bits, said execution unit to select from said first source register at least one of said first and second data elements in response to a first one of said two or more sets of control bits and to copy said selected data element from said first source register to a first data field in a lower half of said destination register, and said execution unit to select from said second source register at least one of said third and fourth data elements in response to a second one of said two or more sets of control bits and to copy said selected data element from said second source register to a second data field in an upper half of said destination register.