High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory

A method of improving performance for a computer processor, said method comprising:

• receiving in an input/output processor data and a memory access instruction from said computer processor, said memory access instruction identifying a type of memory storage task from a group of more than one different memory storage task;
• analyzing said memory access instruction in said input/output processor to identify said type of memory storage task;
• if said type of memory storage task comprises a counter adjustment then
• updating a value containing recent adjustments to said counter in a higher-speed memory, and
• updating a full version of said counter in a slower-speed memory if an overflow of said value containing recent adjustments to said counter occurs;
• and
• if said type of memory storage task comprises a write to a FIFO queue then
• storing said data in a queue tail of said FIFO queue in said higher-speed memory, and
• moving data from said queue tail to a queue body of said FIFO queue in said slower-speed memory if said queue tail is filled
• receiving in an input/output processor, data and multiple memory access instructions from said computer processor;
• said received multiple memory access instructions indicating memory access type pattern from a group of more than one different memory access type patterns that includes a first memory access type pattern and a second memory access type pattern;
• analyzing said received multiple memory access instructions in said input/output processor to identify said memory access type pattern;
• using the input/output processor to perform a first high frequency memory write task and a first low frequency memory write task in response to identification of the first memory access type pattern, wherein data written using the first low frequency memory write task is accessed less frequently than data written using the first high frequency memory write task;
• using the input/output processor to perform a second high frequency memory write task and a second low frequency memory write task in response to identification of the second memory access type pattern, wherein data written using the second low frequency memory write task is accessed less frequently than the second high frequency memory write task;
• if the memory access type pattern is the first memory access type pattern,
• performing the first high frequency memory write task in a higher-speed memory;
• and
• performing the first low frequency memory write task in a slower-speed memory;
• and
• if the memory access type pattern is the second memory access type pattern,
• performing the second high frequency memory write task in the higher-speed memory;
• and
• performing the second low frequency memory write task in the slower-speed memory.