# US RE45,036 E1 · Semiconductor memory device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US RE45,036 E1 - Document ID: USRE45036E1 - Status: Granted - Kind: E1 - Application number: 13/779,097 - Filed: 2013-02-27 - Granted: 2014-07-22 - Earliest claimed: 2005-03-31 - Assignees: Conversant IP N.B. 868 Inc. - Applicants: Conversant IP N.B. 868 Inc. - Inventors: Hee-Bok Kang; Jin-Hong Ahn - Web page: https://patentgrep.com/patent/USRE45036E1 ## Abstract A semiconductor memory device includes a first first-type well including a first cell array for storing a data to apply the data to one of a first bit line and a first bit line bar, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar; a first second-type well including a first sense amplifying MOS transistor having a first-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel for sensing and amplifying the signal difference between the first bit line and the first bit line bar. ## Claims ### Claim 1 A semiconductor memory device having a folded bit line structure and operating with a source voltage and a ground voltage, comprising: a first first-type well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period; a first second-type well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors for sensing and amplifying a signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor and a second connection MOS transistor having a first-type channel for connecting or disconnecting the first bit line and the first bit line bar to or from the first sense amplifying MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel among the plurality of sense amplifying MOS transistors for sensing and amplifying the signal difference between the first bit line and the first bit line bar, each of the first and second first-type wells being supplied with a different bulk voltage. ### Claim 2 (depends on 1) The semiconductor memory device as recited in claim 1, wherein the first bit line and the first bit line bar are floated during the precharge period. ### Claim 3 (depends on 2) The semiconductor memory device as recited in claim 2, wherein the second sense amplifying MOS transistor performs a sensing and amplifying operation by using a low voltage lower than the ground voltage. ### Claim 4 (depends on 3) The semiconductor memory device as recited in claim 3, wherein the first sense amplifying MOS transistor performs a sensing and amplifying operation by using a high voltage higher than the source voltage. ### Claim 5 (depends on 3) The semiconductor memory device as recited in claim 3, wherein the first sense amplifying MOS transistor performs a sensing and amplifying operation by using the source voltage. ### Claim 6 (depends on 2) The semiconductor memory device as recited in claim 2, wherein the first first-type well includes a first auxiliary MOS transistor having a second-type channel for sensing and amplifying a lower voltage level of the first bit line and the first bit line bar, which are located between the first cell array and the first and second connection MOS transistor transistors, as a voltage level of the ground voltage. ### Claim 7 (depends on 6) The semiconductor memory device as recited in claim 6, further comprising a third first-type well including a second cell array for storing data to be applied to one of a second bit line and a second bit line bar selected among the plurality of bit lines, and a second precharge MOS transistor having a second-type channel for equalizing voltage levels of the second bit line and the second bit line bar during the precharge period. ### Claim 8 (depends on 7) The semiconductor memory device as recited in claim 7, wherein the first second-type well includes a second third connection MOS transistor and a fourth connection MOS transistor having a first-type channel for connecting or disconnecting the second bit line and the second bit line bar to or from the first and the second sense amplifying MOS transistors. ### Claim 9 (depends on 8) The semiconductor memory device as recited in claim 8, wherein the third first-type well includes a second auxiliary MOS transistor having a second-type channel for sensing and amplifying a lower voltage level of the second bit line and the second bit line bar, which are located between the second cell array and the second third and fourth connection MOS transistor transistors, as the voltage level of the ground voltage. ### Claim 10 (depends on 9) The semiconductor memory device as recited in claim 9, wherein the second first-type well includes an input/output MOS transistor having a second-type channel for connecting the data sensed and amplified by the first and the second sense amplifying MOS transistors to a local data bus line. ### Claim 11 (depends on 10) The semiconductor memory device as recited in claim 10, wherein the first to third first-type wells, and the first second-type well are formed over a first-type substrate. ### Claim 12 (depends on 11) The semiconductor memory device as recited in claim 11, wherein the first-type substrate includes a second second-type well for wrapping up the first first-type well and a third second-type well for wrapping up the third first-type well. ### Claim 13 (depends on 12) The semiconductor memory device as recited in claim 12, wherein each of the first to the third first-type wells, and the first and the second second-type wells is supplied with a different bulk voltage. ### Claim 14 (depends on 12) The semiconductor memory device as recited in claim 12, wherein the first-type is a P-type and the second-type is an N-type. ### Claim 15 (depends on 12) The semiconductor memory device as recited in claim 12, wherein the first-type is an N-type and the second-type is a P-type. ### Claim 16 A semiconductor memory device having a folded bit line structure and operating with a source voltage and a ground voltage, comprising: a first well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines; a second well including a second cell array for providing data to a second bit line or a second bit line bar selected among the plurality of bit lines; a third well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors provided in a bit line sense amplifier, a first connection unit for connecting or disconnecting the first bit line and the first bit line bar to or from the bit line sense amplifier, and a second connection unit for connecting or disconnecting the second bit line and the second bit line bar to or from the bit line sense amplifier; and a fourth well including a second sense amplifying MOS transistor having a second-type channel among the plurality of sense amplifying MOS transistors provided in the bit line sense amplifier, the third and the fourth wells being supplied with a different bulk voltage. ### Claim 17 (depends on 16) The semiconductor memory device as recited in claim 16, wherein the first well includes a first precharge unit for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period. ### Claim 18 (depends on 17) The semiconductor memory device as recited in claim 17, wherein the second well includes a second precharge unit for equalizing voltage levels of the second bit line and the second bit line bar during the precharge period. ### Claim 19 (depends on 18) The semiconductor memory device as recited in claim 18, wherein the first and the second precharge units float the first and the second bit lines and the first and the second bit line bars during the precharge period. ### Claim 20 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the second sense amplifying MOS transistor performs a sensing and amplifying operation by using a low voltage lower than the ground voltage. ### Claim 21 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the first sense amplifying MOS transistor performs a sensing and amplifying operation by using a high voltage higher than the source voltage. ### Claim 22 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the first sense amplifying MOS transistor performs a sensing and amplifying operation by using the source voltage. ### Claim 23 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the first well includes a first auxiliary unit for sensing and amplifying a lower voltage level of the first bit line and the first bit line bar, which are located between the first cell array and the first connection unit, as a voltage level of the ground voltage. ### Claim 24 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the second well includes a second auxiliary unit for sensing and amplifying a lower voltage level of the second bit line and the second bit line bar, which are located between the second cell array and the second connection unit, as a voltage level of the ground voltage. ### Claim 25 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the fourth well includes a data input/output unit for outputting data sensed and amplified by the bit line sense amplifier through a local data bus line to an external circuit, or for delivering data inputted from the external circuit via the local data bus line to the bit line sense amplifier. ### Claim 26 (depends on 19) The semiconductor memory device as recited in claim 19, wherein the first to the fourth wells are formed over a first-type substrate. ### Claim 27 (depends on 26) The semiconductor memory device as recited in claim 26, wherein the fourth well is wrapped up in the third well. ### Claim 28 (depends on 26) The semiconductor memory device as recited in claim 26, wherein each of the first to the fourth wells is supplied with a different bulk voltage. ### Claim 29 (depends on 26) The semiconductor memory device as recited in claim 26, wherein the first-type is a P-type and the second-type is an N-type. ### Claim 30 (depends on 26) The semiconductor memory device as recited in claim 26, wherein the first-type is an N-type and the second-type is a P-type. ### Claim 31 (depends on 16) The semiconductor memory device as recited in claim 16, wherein: the first connection unit comprises: a first MOS transistor connected in series between the first bit line and a first input of the bit line sense amplifier; and a second MOS transistor connected in series between the first bit line bar and a second input of the bit line sense amplifier; and the second connection unit comprises: a first MOS transistor connected in series between the second bit line and a first input of the bit line sense amplifier; and a second MOS transistor connected in series between the second bit line bar and a second input of the bit line sense amplifier. ### Claim 32 (depends on 31) The semiconductor memory device as recited in claim 31, wherein: the first and second MOS transistors of the first connection unit are PMOS transistors; and the first and second MOS transistors of the second connection unit are PMOS transistors. ### Claim 33 (depends on 16) The semiconductor memory device as recited in claim 16, wherein: the fourth well is wrapped up in the third well. ### Claim 34 (depends on 16) The semiconductor memory device as recited in claim 16, wherein: the first and the second wells are supplied with a bulk voltage different from the bulk voltages of the third and the fourth wells. ### Claim 35 A semiconductor memory device having a folded bit line structure and operating with a source voltage and a ground voltage, comprising: a first first-type well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines, and a first precharge MOS transistor having a second-type channel for equalizing voltage levels of the first bit line and the first bit line bar during a precharge period; a first second-type well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors for sensing and amplifying a signal difference between the first bit line and the first bit line bar, and a first connection MOS transistor and a second connection MOS transistor having a first-type channel for connecting or disconnecting the first bit line and the first bit line bar to or from the first sense amplifying MOS transistor; and a second first-type well including a second sense amplifying MOS transistor having a second-type channel among the plurality of sense amplifying MOS transistors for sensing and amplifying the signal difference between the first bit line and the first bit line bar, the first second-type well being supplied with a variable bulk voltage to vary a threshold voltage of the first and second connection MOS transistors. ### Claim 36 A semiconductor memory device having a folded bit line structure and operating with a source voltage and a ground voltage, comprising: a first well including a first cell array for providing data to a first bit line or a first bit line bar selected among a plurality of bit lines; a second well including a second cell array for providing data to a second bit line or a second bit line bar selected among the plurality of bit lines; a third well including a first sense amplifying MOS transistor having a first-type channel among a plurality of sense amplifying MOS transistors provided in a bit line sense amplifier, a first connection unit for connecting or disconnecting the first bit line and the first bit line bar to or from the bit line sense amplifier, and a second connection unit for connecting or disconnecting the second bit line and the second bit line bar to or from the bit line sense amplifier; and a fourth well including a second sense amplifying MOS transistor having a second-type channel among the plurality of sense amplifying MOS transistors provided in the bit line sense amplifier, the third well being supplied with a variable bulk voltage to vary a threshold voltage of the first and second connection units.