Bus architecture employing varying width uni-directional command bus

A method for communicating between devices attached to a communication bus in a computer system, said communication bus including a command bus portion, said method comprising the steps of:

• requesting control of said command bus portion by a first device attached to said communication bus during a first bus cycle;
• receiving a grant of control of said command portion by said first device during a second bus cycle;
• transmitting command information for a bus command on a first link of said command bus portion from said first device to a repeater unit during a plurality of consecutive bus cycles beginning with a third bus cycle and ending on a fourth bus cycle, said third and fourth bus cycles occurring a respective pre-defined number of cycles after said second bus cycle;
• and
• re-transmitting said command information on a second link of said command bus portion from a repeater unit to second device attached to said communication bus during a fifth bus cycle, said fifth bus cycle occurring a pre-defined number of cycles after said second bus cycle, wherein command information transmitted on said first link during multiple cycles is transmitted on said second link in a single cycle.

A processor for use in a multi-processor computer system, said computer system having a communications bus for communicating among processors and memory, said communications bus having a command bus portion for transmitting commands from an originating processor to other devices attached to the communications bus, said processor comprising:

• a command bus request port for requesting the right to transmit a command on said command bus portion from an arbitrator;
• a command bus grant port for receiving bus grant from said arbitrator;
• a command output port having a plurality N of output pins for transmitting bus commands;
• a command receive port having a plurality M of input pins for receiving bus commands, wherein M>N, the number of input pins M being sufficient to receive a bus command in one bus cycle;
• and
• interface logic for transmitting bus commands on said command output port responsive to receiving bus grant from said arbitrator, wherein a bus command is transmitted from said plurality of output pins during a plurality of consecutive bus cycles beginning with a first cycle occurring a first pre-defined number of bus cycles after said processor receives bus grant and ending with a second bus cycle occurring a second pre-defined number of bus cycles after said processor receives bus grant.

A memory system comprising:

• a memory controller having an interface that includes a plurality of memory subsystem ports;
• a first memory subsystem including:
• a buffer device having a first port and a second port, and
• a plurality of memory devices coupled to the buffer device via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the memory controller via the buffer device;
• and
• a plurality of point-to-point links, each point-to-point link of the plurality of point-to-point links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of point-to-point links including a first point-to-point link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports.

A memory system comprising:

• a controller device;
• a first buffer device having a first interface and a second interface;
• a second buffer device having a first interface and a second interface;
• a first point-to-point link having a first connection to the controller device and a second connection to the first interface of the first buffer device;
• a first plurality of memory devices connected to the second interface of the first buffer device;
• a second point-to-point link having a first connection to the controller device and a second connection to the first interface of the second buffer device;
• and
• a second plurality of memory devices connected to the second interface of the second buffer device.

A memory system comprising:

• a controller device;
• a first and second plurality of buffer devices, each buffer device of the first and second plurality of buffer devices having an interface connected to a respective plurality of memory devices;
• a first and second repeater device;
• a first point-to-point link having a first connection to the controller device and a second connection to the first repeater device;
• a second point-to-point link having a first connection to the controller device and a second connection to the second repeater device;
• a first plurality of repeater links, each repeater link having first connection to a respective buffer device of the first plurality of buffer devices, and a second connection to the first repeater device;
• and
• a second plurality of repeater links, each repeater link having first connection to a respective buffer device of the second plurality of buffer devices and a second connection to the second repeater device.

A memory system comprising:

• a controller device having an interface;
• a first connector, second connector, and third connector;
• a first point-to point link having a first connection to the interface and a second connection to the first connector;
• a second point-to-point link having a first connection to the interface and a second connection to the second connector;
• a third point-to-point link having a first connection to the interface and a second connection to the third connector;
• and
• a first memory subsystem including:
• a buffer device connected to the first connector;
• and
• a plurality of memory devices connected to the buffer device, wherein at least one memory device of the plurality of memory devices transfers data to the controller device via the buffer device.

A memory system comprising:

• a controller device;
• a plurality of buffer devices, each buffer device of the plurality of buffer devices having an interface connected to a respective plurality of memory devices;
• a repeater device;
• a point-to-point link having a first connection to the controller device and a second connection to the repeater device;
• a plurality of repeater links, each repeater link having first connection to a respective buffer device of the plurality of buffer devices, and a second connection to the repeater device.

A memory system comprising:

• a memory controller having an interface that includes a plurality of memory subsystem ports;
• a first memory subsystem including:
• a memory data interface unit having a first port and a second port, and
• a plurality of memory devices coupled to the memory data interface unit via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the memory controller via the memory data interface unit;
• and
• a plurality of point-to-point links, each point-to-point link of the plurality of point-to-point links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of point-to-point links including a first point-to-point link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports.

A memory system comprising:

• a controller device;
• a first memory data interface unit having a first interface and a second interface;
• a second memory data interface unit having a first interface and a second interface;
• a first point-to-point link having a first connection to the controller device and a second connection to the first interface of the first memory data interface unit;
• a first plurality of memory devices connected to the second interface of the first memory data interface unit;
• a second point-to-point link having a first connection to the controller device and a second connection to the first interface of the second memory data interface unit;
• and
• a second plurality of memory devices connected to the second interface of the second memory data interface unit.

A memory system comprising:

• a controller device;
• a plurality of memory data interface units, each memory data interface unit of the plurality of memory data interface units having an interface connected to a respective plurality of memory devices;
• a repeater device;
• a point-to-point link having a first connection to the controller device and a second connection to the repeater device;
• a plurality of repeater links, each repeater link having first connection to a respective memory data interface unit of the plurality of memory data interface units, and a second connection to the repeater device.

A memory system comprising:

• a controller device having an interface;
• a first connector, second connector, and third connector;
• a first point-to point link having a first connection to the interface and a second connection to the first connector;
• a second point-to-point link having a first connection to the interface and a second connection to the second connector;
• a third point-to-point link having a first connection to the interface and a second connection to the third connector;
• and
• a first memory subsystem including:
• a memory data interface unit connected to the first connector;
• and
• a plurality of memory devices connected to the memory data interface unit, wherein at least one memory device of the plurality of memory devices transfers data to the controller device via the memory data interface unit.

A memory system comprising:

• a data switch having an interface that includes a plurality of memory subsystem ports;
• a first memory subsystem including:
• a memory data interface unit having a first port and a second port, and
• a plurality of memory devices coupled to the memory data interface unit via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the data switch via the memory data interface unit;
• and
• a plurality of point-to-point links, each point-to-point link of the plurality of point-to-point links having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of point-to-point links including a first point-to-point link to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports.

A memory system comprising:

• a data switch;
• a first memory data interface unit having a first interface and a second interface;
• a second memory data interface unit having a first interface and a second interface;
• a first point-to-point link having a first connection to the data switch and a second connection to the first interface of the first memory data interface unit;
• a first plurality of memory devices connected to the second interface of the first memory data interface unit;
• a second point-to-point link having a first connection to the data switch and a second connection to the first interface of the second memory data interface unit;
• and
• a second plurality of memory devices connected to the second interface of the second memory data interface unit.

A memory system comprising:

• a controller device;
• a plurality of memory data interface units, each memory data interface unit of the plurality of memory data interface units having an interface connected to a respective plurality of memory devices;
• a data switch;
• a point-to-point link having a first connection to the controller device and a second connection to the data switch;
• a plurality of repeater links, each repeater link having first connection to a respective memory data interface unit of the plurality of memory data interface units, and a second connection to the data switch.

A memory system comprising:

• a data switch having an interface;
• a first connector, second connector, and third connector;
• a first point-to point link having a first connection to the interface and a second connection to the first connector;
• a second point-to-point link having a first connection to the interface and a second connection to the second connector;
• a third point-to-point link having a first connection to the interface and a second connection to the third connector;
• and
• a first memory subsystem including:
• a memory data interface unit connected to the first connector;
• and
• a plurality of memory devices connected to the memory data interface unit, wherein at least one memory device of the plurality of memory devices transfers data to the data switch via the memory data interface unit.

A memory system comprising:

• a data switch having an interface that includes a plurality of memory subsystem ports;
• a first memory subsystem including:
• a memory data interface unit having a first port and a second port, and
• a plurality of memory devices coupled to the memory data interface unit via the second port, wherein data is transferred between at least one memory device of the plurality of memory devices and the data switch via the memory data interface unit;
• and
• a plurality of bidirectional point-to-point data buses, each bidirectional point-to-point data bus of the plurality of bidirectional point-to-point data buses having a connection to a respective memory subsystem port of the plurality of memory subsystem ports, the plurality of bidirectional point-to-point data buses including a first bidirectional point-to-point data bus to connect the first port to a first memory subsystem port of the plurality of memory subsystem ports.

A memory system comprising:

• a data switch;
• a first memory data interface unit having a first interface and a second interface;
• a second memory data interface unit having a first interface and a second interface;
• a first bidirectional point-to-point data bus having a first connection to the data switch and a second connection to the first interface of the first memory data interface unit;
• a first plurality of memory devices connected to the second interface of the first memory data interface unit;
• a second bidirectional point-to-point data bus having a first connection to the data switch and a second connection to the first interface of the second memory data interface unit;
• and
• a second plurality of memory devices connected to the second interface of the second memory data interface unit.

A memory system comprising:

• a controller device;
• a plurality of memory data interface units, each memory data interface unit of the plurality of memory data interface units having an interface connected to a respective plurality of memory devices;
• a data switch;
• a point-to-point link having a first connection to the controller device and a second connection to the data switch;
• a plurality of bidirectional point-to-point data buses, each bidirectional point-to-point data bus having first connection to a respective memory data interface unit of the plurality of memory data interface units, and a second connection to the data switch.

A memory system comprising:

• a data switch having an interface;
• a first connector, second connector, and third connector;
• a first bidirectional point-to point data bus having a first connection to the interface and a second connection to the first connector;
• a second bidirectional point-to-point data bus having a first connection to the interface and a second connection to the second connector;
• a unidirectional memory data bus line having a first connection to the interface and a second connection to the third connector;
• and
• a first memory subsystem including:
• a memory data interface unit connected to the first connector;
• and
• a plurality of memory devices connected to the memory data interface unit, wherein at least one memory device of the plurality of memory devices transfers data to the data switch via the memory data interface unit.