Anti-pirate circuit for protection against commercial integrated circuit pirates

A method of controlling initial operation of an integrated circuit IC that is formed on an integrated circuit IC die, the integrated circuit IC die have an on-chip unique number generator formed thereon, the method comprising:

• prior to the initial operation of the integrated circuit IC, causing the on-chip unique number generator to generate a multi-bit die ID that is unique to the integrated circuit IC die;
• storing the unique multi-bit die ID on the integrated circuit IC die as a multi-bit data string;
• subsequent to storing the multi-bit data string on the integrated circuit IC die, and prior to the initial operation of the integrated circuit IC, causing the on-chip unique number generator to regenerate the unique multi-bit die ID;
• utilizing on-chip comparator circuitry formed on the integrated circuit IC die to compare the regenerated unique multi-bit die ID and the stored multi-bit data string;
• and
• in the event that the comparing step results in a match equal to or greater than a predefined number of bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, providing an enable signal to the integrated circuit IC that is required for the initial operation of the integrated circuit IC;
• and
• in the event that the comparing step results in a match of less than the predefined number of bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, providing a disable signal to the integrated circuit IC to disable the initial operation of the integrated circuit IC, and
• wherein the comparing step is performed entirely on the integrated circuit IC die.

An on-chip system for enabling the initial operation of an integrated circuit IC that is formed as part of an integrated circuit IC die, the system comprising:

• an on-chip unique number generator that is formed on the integrated circuit IC die and that generates a multi-bit die ID that is unique to the integrated circuit IC die;
• a non-volatile memory (NVM) an NVM storage element that is formed on the integrated circuit IC die and that, prior to the initial operation of the integrated circuit IC structure, stores the unique multi-bit die ID as a stored multi-bit data string;
• and
• an on-chip comparator that is formed on the integrated circuit IC die and that, prior to the initial operation of the integrated circuit IC structure, compares the unique multi-bit die ID that has been regenerated by the on-chip unique number generator and the stored multi-bit data string and that generates an enable signal required for the initial operation of the integrated circuit IC only in the event that the comparison results in a match of at least a predefined number of the bits of the regenerated unique multi-bit die ID and the stored multi-bit data string, the entire comparison being performed on the integrated circuit IC die.

An IC comprising:

• an NVM, wherein a first multi-bit number is stored in the NVM;
• a number generator that is configured to generate a second multi-bit number, wherein the second multi-bit number is associated with the IC so us to operate as an identifier for the IC;
• a comparator that is configured to compare corresponding bits from each of the first and second multi-bit numbers and to increment a value with each mismatch between corresponding bits from each of the first and second multi-bit numbers, wherein the comparator is configured to generate a match indicator when there is a match between a predefined number of bits of the first and second multi-bit numbers;
• and
• logic that is configured to output an enable signal that is configured to enable functionality of at least a portion of the IC upon receiving the match indicator.

A method comprising:

• generating a first multi-bit number in an IC, wherein the first multi-bit number is associated with the IC so as to operate as an identifier for the IC;
• retrieving a second multi-bit number from an NVM;
• in the IC, sequentially comparing corresponding bits from the first and second multi-bit numbers over a plurality of clock cycles, wherein at least one comparison is performed during each clock cycle;
• incrementing a value with each mismatch between corresponding bits from each of the first and second multi-bit numbers;
• and
• enabling functionality of at least a portion of the IC when the value reaches a predefined number.

An IC comprising:

• an NVM;
• a number generator for generating multi-bit numbers;
• a multi-bit number selectively stored in the NVM;
• a comparator for comparing in turn the bit value of each bit of a generated multi-bit number to the bit value of a corresponding bit of the multi-bit number stored in the NVM;
• a first output from the comparator indicating whether there is a match between a first predefined number of bits of the generated multi-bit number and the stored multi-bit number;
• logic configured for outputting a first signal enabling functionality of at least a first portion of the IC upon the first output indicating a match;
• a second output from the comparator indicating whether there is a match between a second predefined number of bits of the generated multi-bit number and the stored multi-bit number, wherein the second predefined number of bits is greater than the first predefined number of bits;
• and
• a second signal from the logic enabling functionality of at least a second portion of the IC upon the second output indicating a match.

An IC comprising:

• an NVM;
• a number generator for generating multi-bit numbers;
• a multi-bit number selectively stored in the NVM;
• a comparator for comparing a generated multi-bit number to the multi-bit number stored in the NVM;
• a first output from the comparator indicating whether there is a match between a first predefined number of bits of the generated multi-bit number and the stored multi-bit number;
• logic configured for outputting a first signal enabling functionality of at least a first portion of the IC upon the first output indicating a match;
• a ripple counter connected to the first output of the comparator;
• and
• a clocking circuit that clocks the generated multi-bit number out of the number generator serially, and clocks the stored multi-bit number out of the NVM serially, wherein the comparator compares one bit from each of the multi-bit numbers at each clock, and wherein the ripple counter is incremented each time the first output of the comparator indicates a mismatch.

An IC comprising:

• an NVM having a first identification number stored therein, wherein the first identification number is stored in the NVM during the manufacture of the IC;
• a number generator that is configured to generate a second identification number;
• an identification comparator having:
• a first logic circuit that is coupled to the number generator and the NVM;
• a ripple counter that is coupled to the first logic circuit, wherein the ripple counter is configured to count the number of mismatches between corresponding bits from each of the first and second identification numbers;
• and
• a second logic circuit that is coupled to the ripple counter that is configured to generate an enable signal if there is a match between a predefined number of bits of the first and second identification numbers.