System and method for instruction-level parallelism in a programmable multiple network processor environment

An apparatus for processing instructions in multiple threads in an execution unit, comprising:

• an instruction buffer holding configured to hold a first instruction and a second instruction, the first instruction being associated with a first thread, and the second instruction being associated with a second thread, the first instruction and the second instruction including one or more instruction dependency bits;
• a dependency counter,
• an instruction control unit coupled to said instruction buffer and said dependency counter, said instruction control unit detecting configured to detect the instruction dependency bits and incrementing and decrementing to increment and decrement said dependency counter in response to detecting the instruction dependence bits, said instruction control unit configured to disallow execution of the first instruction if in response to said dependency counter includes including a value less than a threshold value;
• and
• an execution switch coupled to said instruction control unit and said instruction buffer, said execution switch sending configured to send instructions to the execution unit.

A method for processing instructions in multiple threads, comprising:

• receiving a first instruction associated with a first thread;
• determining whether execution of the first instruction depends on execution of a second instruction, the second instruction being associated with a second thread;
• examining a counter logic element associated with the first thread if in response to said determining indicates indicating that the first instruction depends on the execution of the second instruction, wherein the logic element comprises a single bi-state element or a tri-state element;
• decrementing the counter if modifying the logic element in response to said examining indicates indicating that the second instruction has already been executed;
• and
• executing the first instruction;
• and
• suspending the processing of the first thread until said examining indicates that the second instruction has already been executed and then resuming processing.

A method for processing instructions in multiple threads, comprising:

• receiving a first instruction associated with a first thread;
• determining whether execution of a second instruction depends on the execution of the first instruction, the second instruction being associated with a second thread;
• incrementing a counter associated with the second thread if in response to said determining indicates indicating that execution of a second instruction depends on the execution of the first instruction;
• and
• executing the first instruction;
• and
• suspending the processing of the second thread in response to the counter associated with the second thread not exceeding a threshold and resuming the processing of the second thread in response to the counter associated with the second thread exceeding the threshold;
• wherein the first instruction and the second instruction include one or more instruction dependency bits.

A method for processing instructions in multiple threads, comprising:

• receiving a first instruction associated with a first thread, the first instruction including one or more instruction dependency bits;
• determining whether a second thread depends on said first instruction;
• incrementing a counter associated with the second thread if in response to the second thread depends depending on said first instruction;
• loading a second instruction associated with a second thread;
• and
• processing the second instruction in a manner related to the value of the counter associated with the second thread;
• and
• suspending, the processing of the second thread in response to the counter not exceeding a threshold and resuming the processing of the second thread in response to the counter exceeding said threshold.

An apparatus for processing instructions in multiple threads, comprising:

• an instruction buffer configured to hold a first instruction and a second instruction, the first instruction including a dependency indicator and being associated with a first thread, and the second instruction including a dependency indicator and being associated with a second thread;
• an instruction control unit coupled to said instruction buffer;
• a dependency counter coupled to said instruction control unit, said dependency counter associated with the first thread;
• said instruction control unit configured to detect the dependency indicators and change the value of increment and decrement said dependency counter in response to detecting the dependency indicators;
• and
• said instruction control unit configured to disallow execution of the first instruction if in response to said dependency counter includes including a value less than a threshold value.

A method for processing instructions in multiple threads, comprising:

• receiving a first instruction associated with a first thread;
• determining that execution of the first instruction depends on execution of a second instruction, the second instruction being associated with a second thread;
• examining a dependency counter associated with the first thread to determine whether the second instruction has already been executed;
• incrementing the dependency counter in response to said determining indicating that execution of the first instruction depends on execution of the second instruction;
• and
• suspending the processing of the first thread when examining indicates that the dependency counter does not exceed a threshold and resuming the processing after the dependency counter exceeds said threshold,
• wherein the first instruction and the second instruction include one or more instruction dependency bits.