Layout technique for matched resistors on an integrated circuit substrate
AssigneeBroadcom Corporation
InventorDavid A. Sobel
Life of this patent
Estimating the term…
Abstract
Provided a method of reducing impedance variations in an electrical circuit structured and arranged for placement on an integrated circuit (IC) substrate. The method includes forming sets of parallel connected resistors, each set corresponding to one of the impedance devices on the IC. Each set also includes two or more parallel resistor paths, each resistor path including two or more cascaded resistors and has a total impedance value substantially equal to the predetermined impedance value of its corresponding impedance device. Finally, the method includes configuring the sets of parallel resistor paths to form an interdigital structure across the substrate when the electrical circuit is placed on the IC.
Claims32
A method for matching resistor impedances in an electrical a circuit configured for placement on an integrated circuit a substrate, the method comprising:
- determining desired resistor values to be associated with the circuit;
- and
- defining interdigital structures to be formed across the substrate when the circuit is placed thereon, the interdigital structures being formed when independent paths of interconnected resistors split at one point on the substrate and recombine at another point, the independent paths of interconnected resistors being representative of the desired resistor values.
An electrical network, comprising:
- a substrate;
- and
- an interdigital structure formed on the substrate, the interdigital structure having independent paths of interconnected components, at least two of the independent paths meeting each other at at least two points, the independent paths of interconnected components being representative of a desired impedance value.
A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
- determining a desired impedance between the first node and the second node;
- designing the electrical network to have a first component disposed in a first branch between the first node and the second node and to have a second component disposed in a second branch between the first node and the second node, the first and second branches being independent;
- and
- arranging the first component and the second component in an interdigital pattern.
A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
- determining a desired impedance between the first node and the second node;
- designing the electrical network to have a first component disposed in a first branch between the first node and a third node of the electrical network, a second component disposed in a second branch between the first node and the third node, a third component disposed in a third branch between the third node and the second node, and a fourth component disposed in a fourth branch between the third node and the second node, the first, second, third and fourth branches being independent;
- arranging the first component and the second component in a first interdigital pattern;
- and
- arranging the third component and the fourth component in a second interdigital pattern.
An electrical network configured to minimize mismatch characteristics of impedances between a first node of the electrical network and a second node of the electrical network, comprising:
- a first component disposed in a first branch between the first node and the second node;
- and
- a second component disposed in a second branch between the first node and the second node, the first and second branches being independent;
- wherein the first component and the second component are arranged in an interdigital pattern and an impedance between the first node and the second node is a predetermined impedance.
An electrical network configured to minimize mismatch characteristics of impedances between a first node of the electrical network and a second node of the electrical network, comprising:
- a first component disposed in a first branch between the first node and a third node of the electrical network;
- a second component disposed in a second branch between the first node and the third node;
- a third component disposed in a third branch between the third node and the second node;
- and
- a fourth component disposed in a fourth branch between the third node and the second node, the first, second, third and fourth branches being independent;
- wherein an impedance between the first node and the second node is a predetermined impedance, and wherein the first component and the second component are arranged in a first interdigital pattern, and the third component and the fourth component are arranged in a second interdigital pattern.
A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
- forming a first component disposed in a first branch between the first node and the second node;
- and
- forming a second component disposed in a second branch between the first node and the second node, the first and second branches being independent;
- wherein the first component and the second component are arranged in an interdigital pattern and an impedance between the first node and the second node is a predetermined impedance.
A method for minimizing mismatch characteristics of impedances between a first node of an electrical network and a second node of the electrical network, comprising:
- forming a first component disposed in a first branch between the first node and a third node of the electrical network;
- forming a second component disposed in a second branch between the first node and the third node;
- forming a third component disposed in a third branch between the third node and the second node;
- and
- forming a fourth component disposed in a fourth branch between the third node and the second node, the first, second, third and fourth branches being independent;
- wherein an impedance between the first node and the second node is a predetermined impedance, and wherein the first component and the second component are arranged in a first interdigital pattern, and the third component and the fourth component are arranged in a second interdigital pattern.
Dependencies are inferred from the claim text.