Register controlled delay locked loop and its control method
AssigneeHynix Semiconductor Inc.
InventorsJong-Tae Kwak, Hyum-Woo Lee
Life of this patent
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Abstract
A register controlled delay locked loop (DLL), including: a coarse delay line for generating a delayed input clock signal by delaying an external clock signal; a fine delay line unit for receiving the delayed input clock signal in order to generate a first fine delayed clock signal and a second fine delayed clock signal; a phase detector for comparing phases of the external clock signal and a feed-backed clock signal in order to generate a phase detection signal based on the comparison result; a phase mixer for generating a mixed clock signal by mixing phases of the first fine delayed clock signal and the second fine delayed clock signal based on a weight value; and a mixer controller for generating the weight value based on the phase detection signal.
Claims15
A register controlled delay locked loop (DLL), comprising:
- a coarse delay line for generating a delayed input clock signal by delaying an external clock signal;
- a fine delay line unit for receiving the delayed input clock signal in order to generate a first fine delayed clock signal and a second fine delayed clock signal;
- a phase detector for comparing phases of the external clock signal and a feed-backed clock signal in order to generate a phase detection signal based on the comparison result;
- a phase mixer for generating a mixed clock signal by mixing phases of the first fine delayed clock signal and the second fine delayed clock signal based on a weight value;
- and
- a mixer controller for generating the weight value based on the phase detection signal.
A register controlled DLL, comprising:
- a coarse delay line for generating a delayed input clock signal in order to coarsely synchronize a delay locked clock signal with an external clock signal by delaying the external clock signal;
- a first fine delay line for generating a first fine delayed clock signal by delaying the delayed input clock signal;
- and
- a second fine delay line for generating a second fine delayed clock signal by delaying the delayed input clock signal,
- wherein the second fine delay line includes one more unit delay cell than the first fine delay line and more delays or less delays the delayed input clock signal than the first fine delay line by a delay amount of a unit delay cell.
A method for compensating a clock skew between an external clock signal and a mixed clock signal, comprising the steps of:
- a) generating a delayed input clock signal by delaying the external clock signal for coarsely synchronizing the delay locked clock signal with the external clock signal;
- b) generating a plurality of fine delayed clock signals having different phases by delaying the delayed input clock signal;
- and
- c) generating the mixed clock signal by mixing phases of the plurality of fine delayed clock signals.
Dependencies are inferred from the claim text.