Interoperability with multiple instruction sets

A method of switching between a predetermined plurality of instruction sets used by a data processing apparatus, the method comprising:

• in response to a first instruction:
• (i) accessing a sequence of bits, the sequence of bits having an address portion that identifies the location of a second instruction in a memory and an instruction set indicator portion;
• (ii) identifying an instruction set selected from the predetermined plurality of instruction sets based on the instruction set indicator portion of the sequence of bits;
• (iii) setting one or more control flags to indicate that a current instruction set for the data processing apparatus is the instruction set identified based on the instruction set indicator portion of the sequence of bits;
• and
• retrieving the second instruction from the location specified by the address portion of the sequence of bits,
• wherein the instruction set identified by the instruction set indicator portion of the sequence of bits is identifiable without regard to the address specified by the address portion of the sequence of bits.

A method of switching between a predetermined plurality of instruction sets used by a data processing apparatus, the method comprising:

• in response to a first instruction:
• (i) accessing a sequence of bits, the sequence of bits having an address portion that identifies the location of a second instruction in a memory and an instruction set indicator portion, the instruction set indicator portion having at least one bit that is not part of the address portion of the sequence of bits;
• (ii) identifying an instruction set selected from the predetermined plurality of instruction sets based on the instruction set indicator portion of the sequence of bits;
• (iii) setting one or more control flags to indicate that a current instruction set for the data processing apparatus is the instruction set identified based on the instruction set indicator portion of the sequence of bits;
• and
• retrieving the second instruction from the location specified by the address portion of the sequence of bits.

A data processing apparatus capable of operating using instructions from a predetermined plurality of instruction sets, the data processing apparatus comprising:

• (i) a processor core responsive to a first instruction to access a sequence of bits, the sequence of bits having an address portion that specifies the location of a second instruction in a memory and an instruction set indicator portion, the processor core using the instruction set indicator portion of the sequence of bits to set one or more control flags;
• and
• (ii) a controller responsive to the one or more control flags, the state of the one or more control flags specifying a current instruction set selected from the predetermined plurality of instruction sets, to cause the processor core to execute the second instruction as an instruction from the current instruction set,
• wherein the one or more control flags are set without regard to the location of the second instruction.

A data processing apparatus capable of operating using instructions from a predetermined plurality of instruction sets, the data processing apparatus comprising:

• (i) a processor core responsive to a first instruction to access a sequence of bits, the sequence of bits having an address portion that specifies the location of a second instruction in a memory and an instruction set indicator portion and the instruction set indicator portion having at least one bit that is not part of the address portion of the sequence of bits;
• (ii) the processor core using the instruction set indicator portion of the sequence of bits to set one or more control flags, the state of the one or more control flags specifying a current instruction set selected from the predetermined plurality of instruction sets;
• and
• (iii) a controller responsive to the one or more control flags to cause the processor core to execute the second instruction as an instruction from the current instruction set.

A data processing architecture capable of operating using instructions from a predetermined plurality of instruction sets, the data processing architecture comprising:

• (i) a processor core responsive to a first instruction to access a sequence of bits, the sequence of bits having an address portion that specifies the location of a second instruction in a memory and an instruction set indicator portion, the processor core using the instruction set indicator portion of the sequence of bits to set one or more control flags;
• and
• (ii) a controller responsive to the one or more control flags, the state of the one or more control flags specifying a current instruction set selected from the predetermined plurality of instruction sets, to cause the processor core to execute the second instruction as an instruction from the current instruction set,
• wherein the one or more control flags are set without regard to location of the second instruction.

A data processing architecture capable of operating using instructions from a predetermined plurality of instruction sets, the data processing architecture comprising:

• (i) a processor core responsive to a first instruction to access a sequence of bits, the sequence of bits having an address portion that specifies the location of a second instruction in a memory and an instruction set indicator portion and the instruction set indicator portion having at least one bit that is not part of the address portion of the sequence of bits;
• (ii) the processor core using the instruction set indicator portion of the sequence of bits to set one or more control flags, the state of the one or more control flags specifying a current instruction set selected from the predetermined plurality of instruction sets;
• and
• (iii) a controller responsive to the one or more control flags to cause the processor core to execute the second instruction as an instruction from the current instruction set.

A data processing apparatus capable of switching between a predetermined plurality of instruction sets, the data processing apparatus comprising:

• (i) means for accessing a sequence of bits in response to a first instruction, the sequence of bits having an address portion that specifies the location of a second instruction in a memory and an instruction set indicator portion;
• (ii) means for identifying an instruction set selected from the predetermined plurality of instruction sets based on the instruction set indicator portion of the sequence of bits in response to the first instruction;
• (iii) means for setting one or more control flags to indicate that a current instruction set for the data processing apparatus is the instruction set identified based on the instruction set indicator portion of the sequence of bits in response to the first instruction;
• and
• (iv) means for retrieving the second instruction from the location specified by the address portion of the sequence of bits in response to the first instruction,
• wherein the instruction set identified by the instruction set portion of the sequence of bits is identifiable without regard to the location of the second instruction.

A method of operating a data processing apparatus, the method comprising:

• (i) receiving a first instruction from a first instruction set selected from a predetermined plurality of instruction sets;
• (ii) translating the first instruction to generate a first set of one or more control signals;
• (iii) accessing a sequence of bits comprising an address portion that specifies the location of a second instruction in a memory and an instruction set indicator portion in response to the first set of one or more control signals, the instruction set indicator portion having at least one bit that is not part of the address portion of the sequence of bits;
• (iv) setting one or more control flags based upon the value of the instruction set indicator portion of the sequence of bits to specify that a current instruction set is a second instruction set selected from a predetermined plurality of instruction sets;
• (v) retrieving the second instruction from the location specified by the address portion of the sequence of bits;
• and
• (vi) translating the second instruction as an instruction from the current instruction set to generate a second set of one or more control signals.

A method of selecting an instruction set comprising the steps of:

• receiving a branching instruction written in a first instruction set of a plurality of instruction sets;
• in response to the branching instruction, inserting an address of a second instruction, which specifies the location of the second instruction in a memory, into a register and setting the value of a flag, where the value of the flag is not dependent upon the address of the location of the second instruction in the memory;
• selecting an instruction set based upon the value of the flag;
• and
• acquiring the second instruction.

A processing apparatus comprising:

• a pointer for identifying an address, which specifies the location in a memory of a next instruction that is written in a first instruction set of a plurality of instruction sets;
• and
• a flag for identifying the first instruction set;
• wherein:
• the pointer and the flag are both written in response to an instruction from a second instruction set of the plurality of instruction sets, and
• the value of the flag is not dependent upon the address that specifies the location in the memory of the next instruction.