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US RE42,864 E1Granted
Rugged and fast power MOSFET and IGBT
AssigneeIXYS Corporation
InventorsVladimir Tsukanov, Nathan Zommer
Life of this patent
Estimating the term…
Abstract
A power semiconductor device includes a substrate having an upper surface and a lower surface. A source region of first conductivity is formed within a well region of second conductivity. The source region is provided proximate to the upper surface of the substrate. The well region has a non-polygon design. A gate electrode overlies the upper surface of the substrate. A drain electrode is provided proximate to the lower surface of the substrate.
Claims34
A power semiconductor device, comprising:
- a substrate having an upper surface and a lower surface;
- a source region of first conductivity formed within a continuous well region of second conductivity, the source region provided proximate to the upper surface of the substrate, the source region having a first region, a second region, and a third region, the well region having a non-polygon design in a shape of one of a peanut or two overlapping circles;
- first and second gate electrodes overlying the upper surface of the substrate;
- and
- a drain electrode provided proximate to the lower surface of the substrate,
- wherein the first region of the source region and the first gate electrode define a first channel, and the second region of the source region and the second gate electrode define a second channel.,
- wherein the first and second channels are defined within the well region.
4 more elements
A power device, comprising:
- a substrate having an upper surface and a lower surface;
- a plurality of cells provided proximate to the upper surface of the substrate, the cells having non-polygon shapes and including source regions defining narrow electrical path within the cells;
- and
- a drain electrode provided proximate to the lower surface of the surface substrate,
- wherein the source region is formed within a continuous well region having a shape of one of a peanut or two overlapping circles, the source region including a first portion, a second portion, and a third portion, the first portion defining a first circular path, the second portion defining a second circular path, the third portion connecting the first and second circular paths to define a continuous current path.
2 more elements
A power semiconductor device, comprising:
- a substrate having an upper surface and a lower surface;
- a source region of N conductivity formed within a well region of P conductivity, the source region provided proximate to the upper surface of the substrate and having a first circular path, a second circular path, and a connecting portion connecting the first and second circular paths;
- a gate electrode overlying the upper surface of the substrate;
- and
- a drain electrode provided proximate to the lower surface of the substrate,
- wherein the connecting portion is configured to provided an increase resistance in the source region,
- wherein the well region has smooth profiles without angular edges and is formed in a shape of one of a peanut or two overlapping circles.
4 more elements
A power semiconductor device, comprising:
- a substrate having an upper surface and a lower surface;
- a source region of first conductivity formed within a continuous well region of second conductivity, the source region provided proximate to the upper surface of the substrate, the source region having a first region, a second region, and a third region;
- first and second gate electrodes overlying the upper surface of the substrate;
- and
- a drain electrode provided proximate to the lower surface of the substrate,
- wherein the first region of the source region and the first gate electrode define a first channel, and the second region of the source region and the second gate electrode define a second channel.
3 more elements
A power semiconductor device, comprising:
- a substrate having an upper surface and a lower surface;
- a source region of N conductivity formed within a well region of P conductivity having one of a peanut shape or two overlapping circles, and the source region includes two circular regions, the source region provided proximate to the upper surface of the substrate and having a first circular path, a second circular path, and a connecting portion connecting the first and second circular paths;
- a gate electrode overlying the upper surface of the substrate, the gate electrode including an opening having a first circular opening, a second circular opening, and a connecting portion opening, wherein the connecting portion opening has a linear dimension and is configured to provided an increase resistance in the source region;
- and
- a drain electrode provided proximate to the lower surface of the substrate.
2 more elements
A power semiconductor device, comprising:
- a substrate having an upper surface and a lower surface;
- a P-well region formed by using a mask having a non-polygon-shaped opening, the P-well being provided proximate the upper surface of the substrate, wherein the P-well region has a shape of a peanut or two overlapping circles;
- an N-type source region formed within P-well and having a first region, a second region, and a third region;
- at least one gate electrode overlying the upper surface of the substrate;
- and
- a drain electrode provided proximate to the lower surface of the substrate.
3 more elements
Dependencies are inferred from the claim text.