Semiconductor integrated circuit designing method and system using a design rule modification
AssigneeKabushiki Kaisha Toshiba
InventorsToshiya Kotani, Satoshi Tanaka, Soichi Inoue
Life of this patent
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Abstract
A method for designing a semiconductor integrated circuit is provided which comprises compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule to obtain a compacted pattern, predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, obtaining an evaluated value by comparing the predicted pattern with the compacted pattern, deciding whether the evaluated value satisfies a predetermined condition, and modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
Claims28
A method for designing a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:
- compacting a design layout of a semiconductor integrated circuit, using a computer, on the basis of a given design rule of the semiconductor integrated circuit to obtain a compacted pattern;
- predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit, using a computer, on the basis of the compacted pattern;
- obtaining an evaluated value, using a computer, by comparing the predicted pattern with the compacted pattern;
- deciding, using a computer, whether the evaluated value satisfies a predetermined condition;
- and
- modifying the design rule, using a computer, when the evaluated value is decided as not satisfying the predetermined condition.
A system having a computer readable medium including instructions for designing a semiconductor integrated circuit, comprising:
- means for compacting a design layout of a semiconductor integrated circuit on the basis of a given design rule of the semiconductor integrated circuit to obtain a compacted pattern;
- means for predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern;
- means for obtaining an evaluated value by comparing the predicted pattern with the compacted pattern;
- means for deciding whether the evaluated value satisfies a predetermined condition;
- and
- means for modifying the design rule when the evaluated value is decided as not satisfying the predetermined condition.
A non-transitory computer readable storage medium configured to store encoded with a computer program product storing program instructions for causing a computer to compact a design layout of a semiconductor integrated circuit on the basis of a given design rule of the semiconductor integrated circuit to obtain a compacted pattern, causing the computer to predict a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit on the basis of the compacted pattern, causing the computer to obtain an evaluated value by comparing the predicted pattern with the compacted pattern, causing the computer to decide whether the evaluated value satisfies a predetermined condition, and causing the computer to modify the design rule when the evaluated value is decided as not satisfying the predetermined condition the computer providing a modified design layout of a semiconductor integrated circuit based on the modified design rule.
A method for preparing a design rule for a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:
- obtaining a pattern of a design layout, using a computer, on the basis of a given design rule of the semiconductor integrated circuit;
- predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit, using a computer, on the basis of the obtained pattern;
- obtaining an evaluated value, using a computer, by comparing the predicted pattern with the obtained pattern;
- deciding whether the evaluated value satisfies a predetermined condition, using a computer;
- modifying the given design rule, using a computer, when the evaluated value is decided as not satisfying the predetermined condition;
- and
- determining the given design rule as a fixed design rule for the semiconductor integrated circuit, using a computer, when the evaluated value is decided as satisfying the predetermined condition.
A method for designing a layout for a semiconductor integrated circuit, executed by a computer programmed to perform the method, the method comprising:
- obtaining a pattern of a design layout, using a computer, on the basis of a given design rule of the semiconductor integrated circuit;
- predicting a pattern to be formed at a surface area of a wafer for forming the semiconductor integrated circuit, using a computer, on the basis of the obtained pattern;
- obtaining an evaluated value, using a computer, by comparing the predicted pattern with the obtained pattern;
- deciding whether the evaluated value satisfies a predetermined condition, using a computer;
- modifying the given design rule, using a computer, when the evaluated value is decided as not satisfying the predetermined condition;
- determining the given design rule as a fixed design rule for the semiconductor integrated circuit, using a computer, when the evaluated value is decided as satisfying the predetermined condition;
- and
- designing a layout pattern for the semiconductor integrated circuit, using a computer, using the fixed design rule.
Dependencies are inferred from the claim text.