Pinned photodiode photodetector with common pixel transistors and binning capability

A method, comprising:

• generating photocarriers in a photodiode within a pixel during a plurality of time periods;
• accumulating photocarriers in each of a plurality of photocarrier integrators within said pixel such that each photocarrier integrator accumulates photocarriers generated during a time period different from a time period in which other photocarrier integrators accumulate photocarriers;
• and
• sampling said photocarriers from said photocarrier integrators;
• determining a range of an object using said sampled photocarriers.

A method of operating a range finding sensor, the method comprising;

• providing a plurality of photodiodes, each photodiode having a first output port for switchably coupling each respective photodiode to a first photocarrier integrator in a same pixel as said photodiode and a second output port for switchably coupling each photodiode to a second photocarrier integrator in a same pixel as said photodiode;
• generating first photocarriers in said photodiodes in response to light received during a first time period;
• transferring said first photocarriers to respective first photocarrier integrators via said first output ports;
• generating second photocarriers in said photodiodes in response to light received during a second time period;
• and
• transferring said second photocarriers to respective second photocarrier integrators via said second output ports.

A method comprising:

• providing an array of pixels of a CMOS active pixel image sensor, the array comprising a plurality of rows of pinned photodiodes and a plurality of columns of pinned photodiodes, and including first, second, third, and fourth pinned photodiodes in first, second, third, and fourth different rows, respectively, of the plurality of rows;
• providing an in-pixel buffer transistor comprising a gate and coupled between a supply voltage and an output node, wherein the buffer transistor is configured to control a transfer of charge between the supply voltage and the output node in accordance with a voltage applied to the gate;
• providing a first transfer transistor coupled between the first pinned photodiode and the gate, wherein the first transfer transistor is configured to control a transfer of charge between the first pinned photodiode and the gate;
• providing a second transfer transistor coupled between the second pinned photodiode and the gate, wherein the second transfer transistor is configured to control a transfer of charge between the second pinned photodiode and the gate;
• providing a third transfer transistor coupled between a third pinned photodiode and the gate, wherein the third transfer transistor is configured to control a transfer of charge between the third pinned photodiode and the gate;
• providing a fourth transfer transistor coupled between a fourth pinned photodiode and the gate, wherein the fourth transfer transistor is configured to control a transfer of charge between the fourth pinned photodiode and the gate;
• and
• providing a reset transistor coupled to the gate, wherein when the reset transistor is enabled, charge is transferred to the gate.

A method comprising:

• accumulating charge in a first pinned photodiode of a first pixel that occupies a first row of an array of pixels of a CMOS active pixel imager comprising in-pixel buffer transistors;
• transferring charge from the first pinned photodiode directly to a first diffusion region via a first transistor;
• accumulating charge in a second pinned photodiode of a second pixel that occupies a second row, below the first row, of the array;
• transferring charge from the second pinned photodiode directly to the first diffusion region via a second transistor;
• accumulating charge in a third pinned photodiode of a third pixel that occupies a third row, below the second row, of the array;
• transferring charge from the third pinned photodiode directly to a second diffusion region, separate from the first diffusion region, via a third transistor;
• accumulating charge in a fourth pinned photodiode of a fourth pixel that occupies a fourth row, below the third row, of the array;
• transferring charge from the fourth pinned photodiode directly to the second diffusion region via a fourth transistor;
• applying charge from the first diffusion region to a gate of a fifth transistor coupled between a supply voltage and an output;
• and
• applying charge from the second diffusion region to the gate of the fifth transistor, wherein the fifth transistor is common to the first, second, third, and fourth pixels.

A method comprising:

• enabling a CMOS active pixel image sensor to be exposed to light, wherein first, second, third, and fourth pinned photodiodes disposed in first, second, third, and fourth adjacent rows of photodiodes, respectively, of the CMOS active pixel image sensor are configured to generate first, second, third, and fourth charges upon exposure to the light, respectively;
• enabling the first charge to be transferred to a gate of an output transistor via a first transfer transistor between the first pinned photodiode and the gate;
• enabling the second charge to be transferred to the gate via a second transfer transistor between the second pinned photodiode and the gate;
• enabling the third charge to be transferred to the gate via a third transfer transistor between the third pinned photodiode and the gate;
• and
• enabling the fourth charge to be transferred to the gate via a fourth transfer transistor between the fourth pinned photodiode and the gate.

A method comprising:

• providing a device containing a CMOS active pixel image sensor, the sensor comprising an array of pixels and a plurality of pinned photodiodes arranged in rows including at least first, second, third, and fourth separate rows of photodiodes, each pixel including at least one pinned photodiode, the device configured to expose the CMOS active pixel image sensor to light, in response to which each pinned photodiode of the plurality of pinned photodiodes is to generate charge;
• providing a first circuit configured to operate a gate of a first n-channel transfer transistor coupled between a first pinned photodiode of the first row of the plurality of pinned photodiodes and a gate of an n-channel in-pixel buffer transistor, wherein the buffer transistor is coupled between a supply voltage and an output;
• providing a second circuit configured to operate a gate of a second n-channel transfer transistor coupled between a second pinned photodiode of the second row of the plurality of pinned photodiodes and the gate of the buffer transistor;
• providing a third circuit configured to operate a gate of a third n-channel transfer transistor coupled between a third pinned photodiode of the third row of the plurality of pinned photodiodes and the gate of the buffer transistor;
• providing a fourth circuit configured to operate a gate of a fourth n-channel transfer transistor coupled between a fourth pinned photodiode of the fourth row of the plurality of pinned photodiodes and the gate of the buffer transistor;
• and
• providing a fifth circuit configured to operate a gate of an n-channel reset transistor coupled to the gate of the buffer transistor to reset a voltage on the gate of the buffer transistor.

A method comprising:

• exposing a CMOS active pixel imager to light;
• generating signals responsive to the light in an array of pixels of the imager using photodiodes and in-pixel buffer transistors, comprising the steps of:
• activating a first transfer transistor to transfer charge from a first photodiode in a first row of the array to a gate of an in-pixel buffer transistor of the image sensor;
• activating a second transfer transistor to transfer charge from a second photodiode in a second row of the array to the gate;
• activating a third transfer transistor to transfer charge from a third photodiode in a third row of the array to the gate;
• and
• activating a fourth transfer transistor to transfer charge from a fourth photodiode in a fourth row of the array to the gate.