Write-assisted SRAM bit cell
OwnerRichard F. Hobsoninventor
Life of this patent
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Abstract
An SRAM bit cell with cross-coupled inverters has separate write and read buses. Writing is performed through an NMOS pass transistor. Reading is performed through a PMOS transistor. Because the NMOS transistor does not pass a logic 1 as easily as logic 0, assistance is needed to speed up writing of a logic 1 value relative to the time required to write a logic 0 value. An NMOS pre-charge transistor is coupled between the read bus and ground potential; and, a read is performed simultaneously with a write. This conditions the cell by weakening one of the inverters, such that they cross-couple more quickly when a logic 1 value is written into the cell. Alternatively, a single-ended read/write bus can be coupled to the NMOS pass transistor with write-assistance provided by grounding the PMOS pass transistor.
Claims65
A memory bit cell comprising cross-coupled first and second inverters, each one of the inverters further comprising a pull-up transistor and a pull-down transistor having series-connected terminals defining a storage node, a first pass transistor coupled between a write bus and a first one of the storage nodes, a second pass transistor coupled between a read bus and a second one of the storage nodes, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, and a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, wherein one of the first and second pass transistors is an NMOS transistor and the other one of the first and second pass transistors is a PMOS transistor.
A multiple-row and multiple-column memory array comprising a plurality of bit cells, each one of the bit cells further comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor, wherein each write bus is grouped into one of:
- (i) a plurality of high memory parts;
- and,
- (ii) a plurality of low memory parts;
- the memory array further comprising, for each read bus, a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source.
A method of writing a binary digital value asserted on a write bus into a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, and a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, the method comprising:
- (a) turning the first pass transistor on;
- (b) turning the second pass transistor on;
- (c) if the pre-charge transistor is off, turning the pre-charge transistor on;
- and,
- (d) if the pre-charge transistor is on, keeping the pre-charge transistor turned on.
A method of reading onto a read bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a read enable line for controllably switching the second pass transistor on or off, a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, the method comprising:
- (a) turning the first pass transistor off;
- (b) turning the second pass transistor on;
- and,
- (c) initially turning the pre-charge transistor on, then turning the pre-charge transistor off for a brief time interval, then turning the pre-charge transistor on.
A memory bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, wherein one of the first and second pass transistors is an NMOS transistor and the other one of the first and second pass transistors is a PMOS transistor.
A multiple-row and multiple-column memory array comprising a plurality of bit cells, each bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor, wherein each read/write enable line is grouped into one of:
- (i) a plurality of high memory parts;
- and,
- (ii) a plurality of low memory parts.
A method of writing a binary digital value asserted on a read/write bus into a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assisted line for controllably switching the second pass transistor on or off, the method comprising turning the first and second pass transistors on.
A method of reading onto a read/write bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, the method comprising turing the first pass transistor on and turning the second pass transistor off.
A memory array comprising a plurality of pairs of bit cells, each pair of bit cells further comprising:
- (a) first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor;
- and,
- (b) third and fourth inverters cross-coupled to define third and fourth storage nodes, a third pass transistor coupled between the read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line for controllably switching the third pass transistor on or off, the fourth pass transistor further coupled to the write assist line for controllably switching the fourth pass transistor on or off, one of the third and fourth pass transistors being an NMOS transistor and the other one of the third and fourth pass transistors being a PMOS transistor.
A memory array comprising a plurality of pairs of bit cells, each pair of bit cells further comprising:
- (a) first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor;
- and,
- (b) third and fourth inverters cross-coupled to define third and fourth storage nodes, a third pass transistor coupled between a second read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to the read/write enable line for controllably switching the third pass transistor on or off, the fourth pass transistor further coupled to the write assist line for controllably switching the fourth pass transistor on or off, one of the third and fourth pass transistors being an NMOS transistor and the other one of the third and fourth pass transistors being a PMOS transistor.
A memory array comprising a plurality of quadruplets of bit cells, each quadruplet of bit cells further comprising:
- (a) first and second inverters cross-coupled to define first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line for controllably switching the first pass transistor on or off, the second pass transistor further coupled to a write assist line for controllably switching the second pass transistor on or off, one of the first and second pass transistors being an NMOS transistor and the other one of the first and second pass transistors being a PMOS transistor;
- (b) third and fourth inverters cross-coupled to define third and fourth storage nodes, a third pass transistor coupled between the first read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line for controllably switching the third pass transistor on or off, the fourth pass transistor further coupled to the write assist line for controllably switching the fourth pass transistor on or off, one of the third and fourth pass transistors being an NMOS transistor and the other one of the third and fourth pass transistors being a PMOS transistor;
- (c) fifth and sixth inverters cross-coupled to define fifth and sixth storage nodes, a fifth pass transistor coupled between a second read/write bus and a fifth storage node, a sixth pass transistor coupled between the logic low voltage reference signal source and the sixth storage node, the fifth pass transistor further coupled to the first read/write enable time for controllably switching the fifth pass transistor on or off, the sixth pass transistor further coupled to the write assist line for controllably switching the sixth pass transistor on or off, one of the fifth and sixth pass transistors being an NMOS transistor and the other one of the fifth and sixth pass transistors being a PMOS transistor;
- and,
- (d) seventh and eighth inverters cross-coupled to define seventh and eighth storage nodes, a seventh pass transistor coupled between the second read/write bus and the seventh storage node, an eighth pass transistor coupled between the logic low voltage reference signal source and the eighth storage node, the seventh pass transistor further coupled to the second read/write enable line for controllably switching the seventh pass transistor on or off, the eighth pass transistor further coupled to the write assist line for controllably switching the eighth pass transistor on or off, one of the seventh and eighth pass transistors being an NMOS transistor and the other one of the seventh and eighth pass transistors being a PMOS transistor.
A memory cell, comprising:
- a pair of inverters, wherein the pair of inventors comprise a first storage node and a second storage node;
- a first pass transistor coupled between the first storage node and a write bus;
- a write enable line coupled to a switching terminal of the first pass transistor;
- a second pass transistor coupled between the second storage node and a read bus;
- a read enable line coupled to a switching terminal of the second pass transistor;
- a precharge transistor coupled to the read bus;
- and
- a precharge enable signal coupled to a switching terminal of the precharge transistor.
A memory array, comprising:
- a plurality of bit cells, at least one bit cell comprising
- a pair of inverters, wherein the pair of inventors comprise a first storage node and a second storage node,
- a first pass transistor coupled between the first storage node and a write bus,
- a write enable line coupled to a switching terminal of the first pass transistor,
- a second pass transistor coupled between the second storage node and a read bus, and
- a read enable line coupled to a switching terminal of the second pass transistor;
- a precharge transistor coupled to the read bus;
- and
- a precharge enable signal coupled to a switching terminal of the precharge transistor.
A method of writing a binary digit value asserted on a write bus into a memory bit cell, the bit cell comprising first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a read enable line and capable of controllably switching the second pass transistor to be one of on and off, and a pre-charge transistor coupled between the read bus and a logically low voltage reference signal source, the method comprising:
- turning the first pass transistor on;
- turning the second pass transistor on;
- if the pre-charge transistor is off, turning the pre-charge transistor on;
- and,
- if the pre-charge transistor is on, keeping the pre-charge transistor turned on.
A method of reading onto a read bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second inverters defining first and second storage nodes, a first pass transistor coupled between the write bus and the first storage node, a second pass transistor coupled between a read bus and the second storage node, the first pass transistor further coupled to a write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a read enable line and capable of controllably switching the second pass transistor to be one of on and off, and a pre-charge transistor coupled between the read bus and a logic low voltage reference signal source, the method comprising:
- turning the first pass transistor off;
- turning the second pass transistor on;
- and,
- initially turning the pre-charge transistor on, then turning the pre-charge transistor off for a brief interval, then turning the pre-charge transistor on.
A memory bit cell comprising:
- first and second storage nodes;
- a first pass transistor coupled between a read/write bus and the first storage node;
- and
- a second pass transistor coupled between a logically low voltage reference signal source and the second storage node,
- the first pass transistor further coupled to a read/write enable line wherein the read/write enable line is capable of controllably switching the first pass transistor to be one of on and off,
- the second pass transistor further coupled to a write assist line wherein the write assist line is capable of controllably switching the second pass transistor to be one of on and off,
- wherein one of the first and second pass transistors comprises an NMOS transistor and the other one of the first and second pass transistors comprises a PMOS transistor.
A multiple-row and multiple-column memory array comprising:
- a plurality of bit cells, at least one bit cell comprising:
- first and second storage nodes;
- a first pass transistor coupled between a read/write bus and the first storage node;
- and
- a second pass transistor coupled between a logically low voltage reference signal source and the second storage node,
- the first pass transistor further coupled to a read/write enable line wherein the read/write enable line is capable of controllably switching the first pass transistor to be one of on and off,
- the second pass transistor further coupled to a write assist line wherein the write assist line is capable of controllably switching the second pass transistor to be one of on and off,
- wherein one of the first and second pass transistors comprises an NMOS transistor and the other one of the first and second pass transistors comprises a PMOS transistor.
A method of writing a binary digit value asserted on a read/write bus into a memory bit cell, the bit cell comprising first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logically low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, the method comprising:
- turning the first and second pass transistors on.
A method of reading onto a read/write bus a binary digit value stored in a memory bit cell, the bit cell comprising first and second storage nodes, a first pass transistor coupled between the read/write bus and the first storage node, a second pass transistor coupled between a logically low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, the method comprising:
- turning the first pass transistor on and turning the second pass transistor off.
A memory array comprising a plurality of pairs of bit cells, at least one pair of bit cells comprising:
- first and second inverters defining first and second storage nodes, a first pass transistor coupled between a read/write bus and the first storage node, a second pass transistor coupled between a logically low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, one of the first and second pass transistors comprising an NMOS transistor and the other one of the first and second pass transistors comprising the PMOS transistor;
- and
- third and fourth inverters defining third and fourth storage nodes, a third pass transistor coupled between the read/write bus and the third storage node, a fourth pass transistor coupled between the logically low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line and capable of controllably switching the third pass transistor to be one of on and off, the fourth pass transistor further coupled to the write assist line and capable of controllably switching the fourth pass transistor to be one of on and off, one of the third and fourth pass transistors comprising an NMOS transistor and the other one of the third and fourth pass transistors comprising a PMOS transistor.
A memory array comprising a plurality of pairs of bit cells, at least one pair of bit cells comprising:
- first and second inverters defining first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, one of the first and second pass transistors comprising an NMOS transistor and the other one of the first and second pass transistors comprising a PMOS transistor;
- and,
- third and fourth inverters defining third and fourth storage nodes, a third pass transistor coupled between a second read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to the read/write enable line and capable of controllably switching the third pass transistor to be one of on and off, the fourth pass transistor further coupled to the write assist line and capable of controllably switching the fourth pass transistor to be one of on and off, one of the third and fourth pass transistors comprising an NMOS transistor and the other one of the third and fourth pass transistors comprising a PMOS transistor.
A memory array comprising a plurality of quadruplets of bit cells, at least one quadruplet of bit cells comprising:
- first and second inverters defining first and second storage nodes, a first pass transistor coupled between a first read/write bus and the first storage node, a second pass transistor coupled between a logic low voltage reference signal source and the second storage node, the first pass transistor further coupled to a first read/write enable line and capable of controllably switching the first pass transistor to be one of on and off, the second pass transistor further coupled to a write assist line and capable of controllably switching the second pass transistor to be one of on and off, one of the first and second pass transistors comprising an NMOS transistor and the other one of the first and second pass transistors comprising a PMOS transistor;
- third and fourth inverters defining third and fourth storage nodes, a third pass transistor coupled between the first read/write bus and the third storage node, a fourth pass transistor coupled between the logic low voltage reference signal source and the fourth storage node, the third pass transistor further coupled to a second read/write enable line and capable of controllably switching the third pass transistor to be one of on and off, the fourth pass transistor further coupled to the write assist line and capable of controllably switching the fourth pass transistor to be one of on and off, one of the third and fourth pass transistors comprising an NMOS transistor and the other one of the third and fourth pass transistors comprising a PMOS transistor;
- fifth and sixth inverters defining fifth and sixth storage nodes, a fifth pass transistor coupled between a second read/write bus and the fifth storage node, a sixth pass transistor coupled between the logic low voltage reference signal source and the sixth storage node, the fifth pass transistor further coupled to the first read/write enable line and capable of controllably switching the fifth pass transistor to be one of on and off, the sixth pass transistor further coupled to the write assist line and capable of controllably switching the sixth pass transistor to be one of on and off, one of the fifth and sixth pass transistors comprising an NMOS transistor and the other one of the fifth and sixth pass transistors comprising a PMOS transistor;
- and,
- seventh and eighth inverters defining seventh and eighth storage nodes, a seventh pass transistor coupled between the second read/write bus and the seventh storage node, an eighth pass transistor coupled between the logic low voltage reference signal source and the eighth storage node, the seventh pass transistor further coupled to the second read/write enable line and capable of controllably switching the seventh pass transistor to be one of on and off, the eighth pass transistor further coupled to the write assist line and capable of controllably switching the eighth pass transistor to be one of on and off, one of the seventh and eighth pass transistors comprising an NMOS transistor and the other one of the seventh and eighth pass transistors comprising a PMOS transistor.
Dependencies are inferred from the claim text.