Non-volatile memory comprising means for distorting the output of memory cells
AssigneeSTMicroelectronics S.r.l.
InventorMathieu Lisart
Life of this patent
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Abstract
The present invention relates to a non-volatile memory comprising a memory array comprising functional memory cells and non-functional memory cells linked to at least one non-functional word line. A word line address decoder comprises a special decoding section linked to the non-functional word line, for selecting the non-functional word line when a functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells, and distort the reading of the functional memory cells. Application particularly to integrated circuits for smart cards.
Claims55
A method for interfering with the a reading of data in a plurality of functional memory cells of a non-volatile memory array, where the functional memory cells are linked coupled to functional word lines and to bit lines, the bit lines being linked coupled to sense amplifiers, and wherein the a value of a datum read by a sense amplifier in a the respective functional memory cell varies according to the an on or an off state of the respective functional memory cell, which itself state varies according to the a programmed or an erased state condition of the respective functional memory cell, the method comprisingthe steps of :
- providing a plurality of non-functional memory cells linked coupled to the bit lines of the memory array and to at least one non-functional word line for enabling the non-functional memory cells to be selected, and
- when while the functional memory cells are read-selected, simultaneously selecting non-functional memory cells, such that the non-functional memory cells that are in the on state interfere with the distort reading of the functional memory cells that are in the off state, and cause the supply of distorted logic values at output of the sense amplifiers.
A non-volatile memory comprising:
- a word line address decoder;
- a memory array comprising having functional memory cells linked coupled to functional word lines and to bit lines, the bit lines being linked to sense amplifiers, the word lines being linked coupled to a the word line address decoder, the a value of a datum read by a sense amplifier in from at least a respective functional memory cell varying according to the an on or an off state of the respective functional memory cell, which itself varies according to the one of a programmed or an erased state of the memory cell, a memory comprising:
- ;
- a plurality of non-functional memory cells linked coupled to the bit lines of the memory array and to at least one non-functional word line, and
- the word line address decoder including a special decoding section linked coupled to the non-functional word line, configured to select the at least one non-functional word line when a respective functional word line is read-selected, such that non-functional memory cells are selected simultaneously with the functional memory cells being selected and distorting the reading of the functional memory cells.
A memory device comprising:
- a plurality of first memory cells configured to store data;
- and
- a second memory cell configured to output misleading data bits for distorting data stored in at least as it is being read from one of the first memory cells, during an unauthorized attempt to read the memory device, the second memory cell including at least one transistor having a drain and a source coupled to the drain.
A smart card comprising:
- a plurality of first memory cells configured to store data;
- a at least one second memory cell configured to output a bit of misleading data bits datum to a word, the word consisting of comprising data stored in at least one of the first memory cells, during an unauthorized attempt to read the data stored in the smart card;
- and
- logic configured to disable the at least one second memory cell until an unauthorized attempt to read the smart card is detected, the at least one second memory cell being comprised of at least one dummy transistor, and the at least one dummy transistor having:
- a source;
- and
- a drain coupled to the source.
A memory device comprising:
- a plurality of first memory cells configured to store data;
- a second memory cell configured to output misleading data bits to a word, the word consisting of data stored in at least one of the first memory cells, during an unauthorized attempt to read the memory device;
- the first memory cells coupled to a plurality of first word linesand , each one of the first word lines having a first number of the plurality of first memory cells coupled thereto;
- a plurality of bit lines, each one of the bit lines having a second number of the plurality of first memory cells coupled thereto, wherein each one of the first memory cells is coupled to a respective first word line and a respective bit line;
- a plurality of the second memory cells coupled to a second word line each of the second memory cells also being coupled to at least one of the bit lines;
- an address decoder configured to select word lines to be read;
- and
- logic associated with the address decoder configured to read select the second word line to be read during an unauthorized read attempt of data stored in the first plurality of memory cells.
A memory device comprising:
- a first functional memory cell linked coupled to a first bit line;
- a first non-functional memory cell linked coupled to the first bit line;
- and
- selective memory cell reading means, linked coupled to the first bit line, for simultaneously reading the first functional memory cell and the first non-functional memory cell while reading the first functional memory cell when an unauthorized attempt to read the memory device is detected.
A memory device comprising:
- a plurality of word lines;
- a plurality of bit lines;
- a plurality of memory cells, each memory cell coupled to a respective word line of the plurality of word lines and coupled to a respective bit line of the plurality of bit lines;
- and
- a word line selector circuit configured to select a respective first word line of the plurality of word lines during an authorized read of a number of memory cells coupled to the respective first word line and to select the respective first word line and a respective second word line of the plurality of word lines during an unauthorized read of the number of memory cells coupled to the respective first word line.
A method for interfering with reading of data stored in a memory array having a plurality of memory cells, a plurality of word lines and a plurality of bit lines, each memory cell coupled to a respective one of the bit lines and also to a respective one of the word lines, comprising:
- selecting a first word line the plurality of word lines to read a first at least one memory cell coupled to the first word line;
- and
- selecting a second word line of the plurality of word lines while selecting the first word line, to read a second memory cell coupled to the second word line while reading the first memory cell in response to an unauthorized read of the first memory cell.
An circuit for outputting incorrect data from a memory array comprising:
- a plurality of memory cells storing correct data;
- a plurality of word lines and a plurality of bit lines, each memory cell coupled to a respective one of the bit lines and also to a respective one of the word lines;
- means for selecting a first word line the plurality of word lines to read a memory cell coupled to the first word line;
- means for selecting a second word line of the plurality of word lines to read a second memory cell coupled to the second word line at the same time the first word line is selected in response to an unauthorized read of data in the memory array;
- means for putting a combined signal from a memory cell coupled to the first word line and a memory cell coupled to the second word line on the same bit line during an unauthorized read of the data in the memory array.
Dependencies are inferred from the claim text.