Methods and circuitry for built-in self-testing of content addressable memories

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• a search port interface that receives only 1 bit of test data from the BIST controller, other bits being generated internally to the search port interface, so as to limit a number of required global wires.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• a BIST maintenance interface for communicating test data to the CAM core, the BIST maintenance interface having a capability to expand 2 bits of data from the BIST controller to a required width, the capability to expand being configured to limit a number of needed global wires.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein BIST testing of the BIST circuit does not generate matches on all rows in the CAM core so as to enable low-power BIST operation.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search on the CAM core on every cycle through the search port and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein the CAM core is a ternary CAM core that is capable of storing three states.

Content addressable memory (CAM) circuitry with BIST testing capabilities, comprising:

• a plurality of CAM cores;
• a plurality of BIST circuits coupled to each of the CAM cores;
• and
• a single BIST controller being capable of controlling BIST testing of each of the plurality of CAM cores.

A method for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core, comprising:

• a search port for enabling searches of the CAM core;
• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• and
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST search and a BIST write on the CAM core at the same time.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST write at selected times to the CAM core, wherein the BIST controller is capable of performing a BIST search on the BIST write on the CAM core at the same time;
• and
• a maintenance port comparator being coupled between the BIST controller and a data output of the maintenance port, the maintenance port comparator being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintanance port.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a maintenance port for enabling addressing of locations of the CAM core, the maintanance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST write at selected times to the CAM core and performing a BIST search on the CAM core, and wherein the BIST controller is capable of performing the BIST search and the BIST write in a same cycle;
• and
• a maintanance port comparator being coupled between the BIST controller and a data outpupt of the maintanance port, the maintanance port comparator being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintenance port.

A built-in self-test (BIST) circuit for testing a content addressable memory (CAM) core, comprising:

• a maintenance port for enabling addressing of locations of the CAM core, the maintenance port further including writing logic for writing to locations of the CAM core;
• a BIST controller for coordinating BIST testing of the CAM core, the BIST controller being capable of performing a BIST write at selected times to the CAM core and performing another operation on the CAM core, the BIST write is capable of being performed in a same cycle as the another operation;
• and
• a maintenance port comparator being coupled between the BIST controller and a data output of the maintanance port, the maintenance port comparator being configured to compare an expected data generated by the BIST controller with actual data provided from the data output of the maintenance port.

An apparatus for testing a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further comprising means for writing to locations of the CAM core;
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• maintenance port comparing means for comparing an expected data generated by said BIST testing coordinating means with actual data provided from a data output of said addressing enabling means, said maintenance port comparing means being coupled between said BIST testing coordinating means and the data output of said addressing enabling means.

An apparatus for testing a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;
• and
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search.

An apparatus for testing a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• means for receiving test data, tag data, or control signals, or combinations thereof capable of receiving one bit of test data from said BIST testing coordinating means, other bits being generated internally to said receiving means, and capable of limiting a number of required global wires.

An apparatus for testing a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search;
• and
• means for communicating test data to the CAM core, said test data communicating means having a capability to expand two bits of data from said BIST testing coordinating means to a required width, the capability to expand being capable of limiting a number of needed global wires.

An apparatus for testing a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;
• and
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, the BIST write is capable of being performed in a same cycle as the BIST search, wherein BIST testing of the BIST circuit does not generate matches on one or more rows in the CAM core so as to enable lower-power BIST operation.

An apparatus for testing a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;
• and
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search on the CAM core on every cycle through said search enabling means and performing a BIST write at selected times to the CAM core, wherein the BIST write is capable of being performed in a same cycle as the BIST search wherein the CAM core is a ternary CAM core that is capable of storing three states.

An apparatus, comprising:

• one or more CAM cores;
• means for performing a built-in self test BIST coupled to one or more of the CAM cores and capable of testing each of the one or more CAM cores;
• and
• means for controlling said means for performing the BIST.

An apparatus for performing built-in self-test (BIST) testing on a content addressable memory (CAM) core, comprising:

• means for enabling searches of the CAM core;
• means for enabling addressing of locations of the CAM core, said addressing enabling means further including means for writing to locations of the CAM core;
• and
• means for coordinating BIST testing of the CAM core, said BIST testing coordinating means being capable of performing a BIST search and a BIST write on the CAM core at the same time.