Variable clocked scan test circuitry and method
OwnerLaurence H. Cookeinventor
Life of this patent
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Abstract
A technique to reduce the test data volume and number of scan shift clocks per test pattern by combining the scan inputs with existing values in scan chains and inserting them at additional bit positions along the scan chains in order to reduce the number of shift clocks required to achieve required values at plurality of scan bit positions, and by using multiple taps from the scan chains to form a check-sum in order to reduce the number of scan shift clocks to capture test results.
Claims10
A method of testing an integrated circuit (IC) using test vectors containing a multiplicity of care inputs that are applied to at least one scan-chain of said IC, at least one said test vector containing a number of care inputs that is less than a total length of said test vector, wherein a last one of said care inputs occurs prior to a last position of said at least one test vector, each test vector having a corresponding predetermined expected test responses containing a multiplicity of care outputs, said method comprising, for each of said test vectors:
- a. applying said test vector by applying serial data and clocking at least one said scan-chain only until all bits of said at least one said scan-chain that correspond to care inputs of said test vector have been set to values in accordance with said care inputs of said test vector;
- b. operating said IC to capture at least one bit of a response of said IC to said test vector into at least one scan chain of said IC;
- c. reading out at least some bits of said response of said IC to said test vector from said at least one scan-chain of said IC;
- and
- d. comparing the read out bits of said response of said IC to said test vector to bits of said predetermined expected test response corresponding to said test vector to determine a pass or fail status corresponding to said test vector,
- wherein said care output values are read out of a multiplicity of scan positions of said at least one scan-chain of said IC on successive clocks until all said care output values of said predetermined expected test response corresponding to said test vector in said at least one scan chain of said IC are read out.
A method of testing an integrated circuit (IC) using test vectors containing a multiplicity of care inputs that are applied to at least one scan-chain of said IC, each test vector having a corresponding predetermined expected test responses containing a multiplicity of care outputs, said method comprising, for each of said test vectors, the steps of:
- applying said test vector by applying serial data and clocking at least one said scan chain only until all bits of said at least one said scan chain that correspond to care inputs of said test vector have been set to values in accordance with said care inputs of said test vector, wherein said step of applying serial data includes the step of inserting serial data into a multiplicity of scan positions within said at least one said scan-chain, and, wherein said step of inserting serial data into a multiplicity of scan positions is performed for each of said multiplicity of scan positions by applying a combination of a next bit value of said serial data and a present value of a scan bit previous to the scan position;
- operating said IC to capture at least one bit of a response of said IC to said test vector into at least one scan chain of said IC;
- reading out at least some bits of said response of said IC to said test vector from said at least one scan-chain of said IC;
- and
- comparing the read out bits of said response of said IC to said test vector to bits of said predetermined expected test response corresponding to said test vector to determine a pass or fail status corresponding to said test vector, wherein at least one value of said care inputs for at least one of said test vectors is set by using at least one captured response to a prior test vector.
Dependencies are inferred from the claim text.